An integrated circuit may include an inverter which may include a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in parallel with the first transistor. An input of the inverter may be capable of receiving an oscillating input signal, and which may include an output of the inverter, which is connected to a capacitive device capable of being charged and discharged depending on the state of the first and second transistors being on or off. The inverter may be capable of delivering an oscillating output signal at its output. The integrated circuit may include a selector for transmitting the oscillating output signal and for masking the charging and/or discharging of the capacitive device.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit comprising: a first inverter comprising a first transistor of a first conductivity type, a second transistor of a second conductivity type coupled in parallel with the first transistor, an input configured to receive an oscillating input signal, and an output configured to deliver an oscillating output signal, said first and second transistors each comprising a control terminal coupled to said input of said first inverter and a conduction terminal coupled to the output of said first inverter, said first transistor comprising a second conduction terminal to be coupled to a reference voltage, and said second transistor comprising a second conduction terminal to be coupled to a supply voltage; a capacitive device coupled to said output of said first inverter and capable of being charged and discharged depending on the state of the first and second transistors being on or off; and a selector configured to transmit the oscillating output signal and configured to mask at least one of the charging and discharging of said capacitive device, said selector comprising a second inverter comprising a third transistor of the first conductivity type, a fourth transistor of the second conductivity type coupled in parallel with said third transistor, and an output, said third and fourth transistors each comprising a control terminal coupled to said input of said first inverter and a conduction terminal coupled to the output of said second inverter, said fourth transistor comprising a second conduction terminal to be coupled to the supply voltage, said third transistor comprising a second conduction terminal coupled to the output of said first inverter.
2. The integrated circuit according to claim 1 wherein each of said first and second transistors comprises a metal oxide semiconductor field effect transistor (MOSFET).
3. The integrated circuit according to claim 1 wherein said first inverter further comprises: a fifth transistor of the first conductivity type and comprising a control terminal coupled to the input of said first inverter, a conduction terminal coupled to the output of said first inverter, and a second conduction terminal coupled to the first conduction terminal of said first transistor of said first inverter.
4. An integrated circuit comprising: a first inverter comprising a first transistor of a first conductivity type, a second transistor of a second conductivity type coupled in parallel with the first transistor, an input configured to receive an oscillating input signal, and an output configured to deliver an oscillating output signal, a capacitive device coupled to said output of said first inverter and capable of being charged and discharged depending on the state of the first and second transistors being on or off; and a selector configured to transmit the oscillating output signal and configured to mask at least one of the charging and discharging of said capacitive device, wherein said selector comprises: a third inverter comprising a sixth transistor of the first conductivity type, a seventh transistor of the second conductivity type coupled in parallel with the sixth transistor, and an output, said sixth and seventh transistors each comprising a control terminal coupled to the input of said first inverter and a first conduction terminal coupled to the output of the third inverter, said seventh transistor comprising a second conduction terminal coupled to the output of the first inverter, said sixth transistor further comprising a second conduction terminal to be coupled to a reference voltage.
5. A ring oscillator circuit comprising: an odd number of integrated circuits each comprising a first inverter comprising a first transistor of a first conductivity type, a second transistor of a second conductivity type coupled in parallel with the first transistor, an input configured to receive an oscillating input signal, and an output configured to deliver an oscillating output signal, a capacitive device coupled to said output and capable of being charged and discharged depending on the state of the first and second transistors being on or off, and a selector configured to transmit the oscillating output signal and configured to mask at least one of the charging and discharging of said capacitive device; said odd number of integrated circuits being mounted in series so that the input of said first inverter of one of said odd number of integrated circuits is coupled to an output of said selector of a neighboring one of said odd number of integrated circuits in the series.
6. A measuring circuit configured to measure performance parameters of at least one transistor of an integrated circuit comprising a first inverter comprising a first transistor of a first conductivity type, a second transistor of a second conductivity type coupled in parallel with the first transistor, an input configured to receive an oscillating input signal, and an output configured to deliver an oscillating output signal, the circuit further comprising a capacitive device coupled to the output and capable of being charged and discharged depending on the state of the first and second transistors being on or off, and a selector configured to transmit the oscillating output signal and configured to mask at least one of the charging and discharging of the capacitive device, the measuring circuit comprising: an additional integrated circuit comprising an eighth transistor of the second conductivity type comprising a control terminal configured to receive a pre-charge signal reset to a high voltage, a first conduction terminal to be coupled to a supply voltage, and a second conduction terminal coupled to a pre-charge signal reset to a low voltage, and a ninth transistor of the first conductivity type comprising a control terminal coupled to said second conduction terminal of said eighth transistor, a first conduction terminal to be coupled to a reference voltage, and a second conduction terminal coupled to the control terminal of said eighth transistor.
7. The measuring circuit according to claim 6 further comprising: a second additional integrated circuit comprising a tenth transistor of the second conductivity type comprising a control terminal coupled to the pre-charge signal reset to a low voltage, and a first conduction terminal coupled to the pre-charge signal reset to a high voltage, an eleventh transistor of the first conductivity type comprising a control terminal coupled to the pre-charge signal reset to a high voltage and a first conduction terminal coupled to the pre-charge signal reset to a low voltage, a twelfth transistor of the first conductivity type comprising a control terminal to be coupled to the reference voltage, a first conduction terminal coupled to said first conduction terminal of the tenth transistor, and a second conduction terminal coupled to a first input voltage, and a thirteenth transistor of the first conductivity type comprising a control terminal to be coupled to the reference voltage, a first conduction terminal coupled to the first conduction terminal of said eleventh transistor, and a second conduction terminal coupled to a second input voltage.
8. The measuring circuit according to claim 6 further comprising: a plurality of further additional integrated circuits coupled in parallel so that the pre-charge signal reset to a high voltage of each additional and each of said plurality of further additional integrated circuits are coupled to a first common pre-charge signal reset to a high voltage, and wherein the supply voltage for each additional and each of said plurality of further additional integrated circuits are coupled to a common supply voltage, the pre-charge signals reset to a low voltage of each additional integrated circuit are coupled to a second common pre-charge signal reset to a low voltage; and a pre-charger configured to detect an inversion of at least one common pre-charge signal and configured to reset the common pre-charge signals at each inversion of at least one common pre-charge signal.
9. A telephone system comprising: an inverter comprising a first transistor of a first conductivity type, a second transistor of a second conductivity type coupled in parallel with the first transistor, an input configured to receive an oscillating input signal, and an output configured to deliver an oscillating output signal, said first and second transistors each comprising a control terminal coupled to said input of said first inverter and a conduction terminal coupled to the output of said first inverter, said first transistor comprising a second conduction terminal to be coupled to a reference voltage, and said second transistor comprising a second conduction terminal to be coupled to a supply voltage, a capacitive device coupled to said output of said first inverter and capable of being charged and discharged depending on the state of the first and second transistors being on or off, and a selector configured to transmit the oscillating output signal and configured to mask at least one of the charging and discharging of said capacitive device, said selector comprising a second inverter comprising a third transistor of the first conductivity type, a fourth transistor of the second conductivity type coupled in parallel with said third transistor, and an output, said third and fourth transistors each comprising a control terminal coupled to said input of said first inverter and a conduction terminal coupled to the output of said second inverter, said fourth transistor comprising a second conduction terminal to be coupled to the supply voltage, said third transistor comprising a second conduction terminal coupled to the output of said first inverter.
10. A method configured to measure the performance parameters of at least one transistor of an inverter having a first transistor of a first conductivity type and a second transistor of a second conductivity type, an input of the inverter being configured to receive an oscillating input signal, the method comprising: charging and discharging a capacitive device depending on a state of the first and second transistors being on or off; delivering an oscillating output signal at an output of the inverter; masking at least one of the charging and discharging of the capacitive device; pre-charging to opposite initial voltages, a third transistor of the first conductivity type and fourth transistor of the second conductivity type to turn off the third and fourth transistors; and resetting the pre-charging when at least one of the voltages is inverted with respect to its initial value.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 18, 2009
October 25, 2011
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