A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip. A jumping wire electrically connecting the isolated inner lead and the external lead is adjacent to the second side to achieve the redistribution of pin assignments without affecting wire-bonding. Especially, this package can be applied for multi-chip stacking.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor package primarily comprising: an encapsulant; a leadframe segment having a plurality of leads, an isolated inner lead, and an external lead, wherein the isolated inner lead is completely encapsulated inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant; wherein each lead has an internal portion encapsulated inside the encapsulant and an external portion extended outside the encapsulant and integrally connected with the internal portion, wherein at least one of the internal portions is located between the isolated inner lead and the external lead; a first chip disposed on the leadframe segment and encapsulated by the encapsulant, wherein the first chip has a plurality of first electrodes; wherein each internal portion has a first finger; wherein the isolated inner lead has a second finger and a third finger at two opposing ends thereof; wherein the external lead has a fourth finger; wherein the first fingers and the second finger are arranged along a first side of the first chip without covered by the first chip and the third finger and the fourth finger are arranged along a second side of the first chip without covered by the first chip; a plurality of first bonding wires encapsulated by the encapsulant, wherein the first bonding wires electrically connect the first electrodes of the first chip to the first fingers of the internal portions and to the second finger of the isolated inner lead; and a jumping wire encapsulated by the encapsulant, wherein the jumping wire electrically connects the third finger of the isolated inner lead to the fourth finger of the external lead overpassing the interposing one of the internal portions, wherein the isolated inner lead and the internal portions are formed from a horizontal layer of the leadframe segment; and wherein a back surface of the first chip is attached to the internal portions and the isolated inner lead.
2. The semiconductor package as claimed in claim 1 , further comprising an adhesive film in the encapsulant, the adhesive film attached to the leadframe segment to mechanically fix the isolated inner lead and the internal portions.
3. The semiconductor package as claimed in claim 1 , further comprising a layer of first die attach material disposed on a back surface of the first chip for bonding to the leadframe segment.
4. The semiconductor package as claimed in claim 3 , wherein the fourth finger of the external lead inwardly extends onto the back surface of the first chip, and wherein the first die attach material adheres to the inwardly extending portion of the fourth finger.
5. The semiconductor package as claimed in claim 1 , wherein the jumping wire is adjacent to the second side of the first chip.
6. The semiconductor package as claimed in claim 5 , wherein the jumping wire is approximately parallel to the second side of the first chip.
7. The semiconductor package as claimed in claim 1 , further comprising a second chip disposed on the first chip.
8. The semiconductor package as claimed in claim 7 , further comprising a layer of second die attach material disposed on the second chip for bonding to the first chip.
9. The semiconductor package as claimed in claim 8 , wherein the second chip is stepwise disposed on the first chip to have a lateral extrusion exceeding the second side of the first chip, wherein the jumping wire is hidden under the lateral extrusion.
10. The semiconductor package as claimed in claim 9 , wherein the second die attach material further covers a bottom of the lateral extrusion.
11. The semiconductor package as claimed in claim 1 , wherein the leadframe segment further includes a plurality of short leads shorter than the leads so that the first chip is not disposed on the short leads.
12. The semiconductor package as claimed in claim 11 , wherein the first side and the second side of the first chip are parallel to each other with a plurality of internal terminals of the short leads facing the first side.
13. The semiconductor package as claimed in claim 1 , wherein the first side and the second side of the first chip are perpendicular to each other.
14. The semiconductor package as claimed in claim 13 , wherein the external portions of the leads are disposed at two opposing and parallel sides of the encapsulant.
15. The semiconductor package as claimed in claim 1 , wherein the leadframe segment further includes a plurality of side-supporting pads arranged at two opposing sides of the internal portions of the leads.
16. The semiconductor package as claimed in claim 15 , wherein the side-supporting pads have a plurality of moldflow through holes to be filled with the encapsulant.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 24, 2008
November 1, 2011
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