Internal voltage generator of semiconductor device

1. An internal voltage generator of a semiconductor device, comprising: a charge pumping unit configured to receive an external power supply voltage, to perform a charge pumping operation on the basis of the voltage level of a reference voltage and to generate a charge-pumped voltage; and an internal voltage generating unit configured to receive the charge-pumped voltage, to perform a charge pumping operation on the basis of an internal voltage level that is linear to a temperature change in a first temperature range to generate an internal voltage, and to perform a charge pumping operation on the basis of an internal voltage clamping level that is constant regardless of a temperature change in a second temperature range to generate the internal voltage, wherein the charge-pumped voltage is charge pumped to have a first voltage level higher than the received external power supply voltage when the received external power supply voltage reaches a minimum operation voltage of the semiconductor device.

2. The internal voltage generator of claim 1 , wherein the internal voltage generating unit includes: a first voltage detecting unit configured to receive the charge pumped voltage to detect the internal voltage level that is linearly dependent on the temperature change; a second voltage detecting unit configured to receive the charge pumped voltage to detect the internal voltage clamping level that is constant with respect to the temperature change; a detection signal combining unit configured to combine a first detection signal and a second detection signal outputted from the first voltage detecting unit and the second voltage detecting unit to generate a combined detection signal detecting the internal voltage level with an internal voltage detection level that changes linearly in the first temperature range and an internal voltage clamping level that is constant in the second temperature range; and an internal voltage generator unit configured to generate the internal voltage in a charge pumping mode in response to the combined detection signal.

3. The internal voltage generator of claim 2 , further comprising: a reference voltage generating unit configured to receive the external power supply voltage to generate the reference voltage that always maintains a predetermined target level regardless of a temperature change and a voltage level change of the external power supply voltage.

4. The internal voltage generator of claim 2 , wherein the charge pumped voltage generating unit includes: a charge pumped voltage detector configured to detect the voltage level of the charge pumped voltage on the basis of the voltage level of the reference voltage; a charge pumped voltage oscillator configured to output a charge pumped voltage oscillation signal with a predetermined oscillation frequency in response to the output signal of the charge pumped voltage detector; a charge pump controller configured to receive the charge pumped voltage oscillation signal to generate a charge pump control signal; and a charge pump configured to perform a positive charge pumping operation on a charge pumped voltage output terminal in response to the charge pump control signal.

5. The internal voltage generator of claim 2 , wherein the second temperature range is lower than the first temperature range.

6. The internal voltage generator of claim 2 , wherein the second temperature range is higher than the first temperature range.

7. The internal voltage generator of claim 2 , wherein the internal voltage generating unit includes: an oscillator configured to output an oscillation signal with a predetermined oscillation frequency by using the combined detection signal as an enable signal; a pump controller configured to receive the oscillation signal to generate a pump control signal; and a charge pump configured to perform a negative charge pumping operation on a back-bias voltage output terminal in response to the pump control signal.

8. The internal voltage generator of claim 7 , wherein the first voltage detecting unit includes: a first PMOS transistor having a gate connected to receive a ground voltage, a source and a bulk connected to receive the charge pumped voltage, and a drain connected to a first detection node; an NMOS transistor having a gate connected to receive the charge pumped voltage, a source and a bulk connected to receive a back-bias voltage, and a drain connected to the first detection node; and a first inverter having an input terminal connected to the first detection node to output a first detection signal.

9. The internal voltage generator of claim 8 , wherein the second voltage detecting unit includes: a second PMOS transistor having a gate connected to receive the ground voltage, a source and a bulk connected to receive the charge pumped voltage, and a drain connected to a second detection node; a third PMOS transistor having a gate connected to receive the back-bias voltage, a drain connected to receive the ground voltage, a bulk connected to receive the charge pumped voltage, and a source connected to the second detection node; and a second inverter having an input terminal connected to the second detection node to output a second detection signal.

10. An internal voltage generator of a semiconductor device, comprising: a charge pumping unit configured to receive an external power supply voltage, to perform a charge pumping operation on the basis of the voltage level of a reference voltage and to generate a charge pumped voltage; and an internal voltage generating unit configured to receive the charge pumped voltage to perform a charge pumping operation on the basis of an internal voltage level linear to a temperature change in a first temperature range to generate an internal voltage, to perform a charge pumping operation on the basis of an internal voltage lowest clamping level that is constant regardless of a temperature change in a second temperature range lower than the first temperature range to generate the internal voltage, and to perform a charge pumping operation on the basis of an internal voltage highest clamping level that is constant regardless of a temperature change in a third temperature range higher than the first temperature range to generate the internal voltage, wherein the charge-pumped voltage is charge pumped to have a first voltage level higher than the received external power supply voltage when the received external power supply voltage reaches a minimum operation voltage of the semiconductor device.

11. The internal voltage generator of claim 10 , wherein the internal voltage generating unit includes: a first voltage detecting unit configured to receive the charge pumped voltage to detect the internal voltage level that is linearly dependent on the temperature change; a second voltage detecting unit configured to receive the charge pumped voltage to detect the internal voltage lowest clamping level that is constant regardless of the temperature change; a third voltage detecting unit configured to receive the charge pumped voltage to detect the internal voltage highest clamping level that is constant regardless of the temperature change; a detection signal combining unit configured to combine a first detection signal, a second detection signal, and a third detection signal outputted from the first voltage detecting unit, the second voltage detecting unit, and the third voltage detecting unit to generate a combined detection signal detecting the internal voltage level with an internal voltage detection level that changes linearly in the first temperature range, the internal voltage lowest clamping level that is constant in the second temperature range, and the internal voltage highest clamping level that is constant in the third temperature range; and an internal voltage generator unit configured to generate the internal voltage in a charge pumping mode in response to the combined detection signal.

12. The internal voltage generator of claim 11 , further comprising: a reference voltage generating unit configured to receive the external power supply voltage to generate the reference voltage that maintains a predetermined target level regardless of a temperature change and a voltage level change of the external power supply voltage.

13. The internal voltage generator of claim 11 , wherein the charge pump unit includes: a charge pumped voltage detector configured to detect the voltage level of the charge pumped voltage on the basis of the voltage level of the reference voltage; a charge pumped voltage oscillator configured to output a charge pumped voltage oscillation signal with a predetermined oscillation frequency in response to the output signal of the charge pumped voltage detector; a charge pump controller configured to receive the charge pumped voltage oscillation signal to generate a charge pump control signal; and a charge pump configured to perform a positive charge pumping operation on a charge pumped voltage output terminal in response to the charge pump control signal.

14. The internal voltage generator of claim 11 , wherein the internal voltage generating unit includes: an oscillator configured to output an oscillation signal with a predetermined oscillation frequency by using the combined detection signal as an enable signal; a pump controller configured to receive the oscillation signal to generate a pump control signal; and a charge pump configured to perform a negative charge pumping operation on a back-bias voltage output terminal in response to the pump control signal.

15. The internal voltage generator of claim 14 , wherein the first voltage detecting unit includes: a first PMOS transistor having a gate connected to receive a ground voltage, a source and a bulk connected to receive the charge pumped voltage, and a drain connected to a first detection node; an NMOS transistor having a gate connected to receive the charge pumped voltage, a source and a bulk connected to receive a back-bias voltage, and a drain connected to the first detection node; and a first inverter having an input terminal connected to the first detection node to output the first detection signal.

16. The internal voltage generator of claim 15 , wherein the second voltage detecting unit includes: a second PMOS transistor having a gate connected to receive the ground voltage, a source and a bulk connected to receive the charge pumped voltage, and a drain connected to a second detection node; a third PMOS transistor having a gate connected to receive the back-bias voltage, a drain connected to receive the ground voltage, a bulk connected to receive the charge pumped voltage, and a source connected to the second detection node; and a second inverter having an input terminal connected to the second detection node to output the second detection signal.

17. The internal voltage generator of claim 16 , wherein the third voltage detecting unit includes: a fourth PMOS transistor having a gate connected to receive the ground voltage, a source and a bulk connected to receive the charge pumped voltage, and a drain connected to a third detection node; a fifth PMOS transistor having a gate connected to receive the back-bias voltage, a drain connected to receive the ground voltage, a bulk connected to receive the charge pumped voltage, and a source connected to the third detection node; and a third inverter having an input terminal connected to the third detection node to output the third detection signal.

18. An internal voltage generator of a semiconductor device, comprising: a charge pumping unit configured to receive an external power supply voltage to perform a charge pumping operation on the basis of the voltage level of a reference voltage to generate a charge pumped voltage having a voltage level higher than the external power supply voltage; and an internal voltage generating unit configured to receive the charge pumped voltage to perform a charge pumping operation on the basis of an internal voltage level that is linear with respect to a temperature change in a first temperature range in a first operation mode selectable according to a test signal and a fuse option to generate an internal voltage, to perform a charge pumping operation on the basis of an internal voltage lowest clamping level that is constant regardless of a temperature change in a second temperature range lower than the first temperature range to generate the internal voltage, to perform a charge pumping operation on the basis of an internal voltage highest clamping level that is constant regardless of a temperature change in a third temperature range higher than the first temperature range to generate the internal voltage, and to perform a charge pumping operation on the basis of an internal voltage target level that is constant regardless of the temperature change in all of the first to third temperature ranges in a second operation mode selectable according to the test signal and the fuse option to generate the internal voltage, the internal voltage target level being higher than the constant internal voltage lowest clamping level and lower than the constant internal voltage highest clamping level, wherein the charge-pumped voltage is charge pumped to have a first voltage level higher than the received external power supply voltage when the received external power supply voltage reaches a minimum operation voltage of the semiconductor device.

19. The internal voltage generator of claim 18 , wherein the internal voltage generating unit comprises: a first voltage detecting unit configured to receive the charge pumped voltage to detect the internal voltage level that is linearly dependent on the temperature change; a second voltage detecting unit configured to receive the charge pumped voltage to detect the internal voltage lowest clamping level that is constant regardless of the temperature change; a third voltage detecting unit configured to receive the charge pumped voltage to detect the internal voltage highest clamping level that is constant regardless of the temperature change; a fourth voltage detecting unit configured to receive the charge pumped voltage to detect the internal voltage target level that is constant regardless of the temperature change, the internal voltage target level being higher than the constant internal voltage lowest clamping level and lower than the constant internal voltage highest clamping level; a first selecting unit configured to output a first detection signal outputted from the first voltage detecting unit or a fourth detection signal outputted from the fourth voltage detecting unit as an uncombined detection signal according to a first fuse option and a first test signal; a detection signal combining unit configured to combine the uncombined detection signal, a second detection signal outputted from the second voltage detecting unit, and a third detection signal outputted from the third voltage detecting unit to generate a combined detection signal detecting the internal voltage level with an internal voltage detection level that changes linearly in the first temperature range, the internal voltage lowest clamping level that is constant in the second temperature range, and the internal voltage highest clamping level that is constant in the third temperature range; a second selecting unit configured to output the uncombined detection signal or the combined detection signal as an enable signal according to a second fuse option and a second test signal; and an internal voltage generator unit configured to generate the internal voltage in a charge pumping mode in response to the enable signal.

20. The internal voltage generator of claim 19 , further comprising a reference voltage generating unit configured to receive the external power supply voltage to generate the reference voltage that maintains a predetermined target level regardless of a temperature change and a voltage level change of the external power supply voltage.

21. The internal voltage generator of claim 19 , wherein the charge pumping unit includes: a charge pumped voltage detector configured to detect the voltage level of the charge pumped voltage on the basis of the voltage level of the reference voltage; a charge pumped voltage oscillator configured to output a charge pumped voltage oscillation signal with a predetermined oscillation frequency in response to the output signal of the charge pumped voltage detector; a charge pump controller configured to receive the charge pumped voltage oscillation signal to generate a charge pumping power supply voltage pump control signal; and a charge pump configured to perform a positive charge pumping operation on a pumping power supply voltage output terminal in response to the charge pump control signal.

22. The internal voltage generator of claim 19 , wherein the internal voltage generating unit includes: an oscillator configured to output an oscillation signal with a predetermined oscillation frequency by using the combined detection signal as an enable signal; a pump controller configured to receive the oscillation signal to generate a pump control signal; and a charge pump configured to perform a negative charge pumping operation on a back-bias voltage output terminal in response to the pump control signal.

23. The internal voltage generator of claim 22 , wherein the first voltage detecting unit includes: a first PMOS transistor having a gate connected to receive a ground voltage, a source and a bulk connected to receive the charge pumped voltage, and a drain connected to a first detection node; an NMOS transistor having a gate connected to receive the charge pumped voltage, a source and a bulk connected to receive a back-bias voltage, and a drain connected to the first detection node; and a first inverter having an input terminal connected to the first detection node to output the first detection signal.

24. The internal voltage generator of claim 23 , wherein the second voltage detecting unit includes: a second PMOS transistor having a gate connected to receive the ground voltage, a source and a bulk connected to receive the charge pumped voltage, and a drain connected to a second detection node; a third PMOS transistor having a gate connected to receive the back-bias voltage, a drain connected to receive the ground voltage, a bulk connected to receive the charge pumped voltage, and a source connected to the second detection node; and a second inverter having an input terminal connected to the second detection node to output the second detection signal.

25. The internal voltage generator of claim 24 , wherein the third voltage detecting unit includes: a fourth PMOS transistor having a gate connected to receive the ground voltage, a source and a bulk connected to receive the charge pumped voltage, and a drain connected to a third detection node; a fifth PMOS transistor having a gate connected to receive the back-bias voltage, a drain connected to receive the ground voltage, a bulk connected to receive the charge pumped voltage, and a source connected to the third detection node; and a third inverter having an input terminal connected to the third detection node to output the third detection signal.

26. The internal voltage generator of claim 25 , wherein the fourth voltage detecting unit includes: a sixth PMOS transistor having a gate connected to receive the ground voltage, a source and a bulk connected to receive the charge pumped voltage, and a drain connected to a fourth detection node; a seventh PMOS transistor having a gate connected to receive the back-bias voltage, a drain connected to receive the ground voltage, a bulk connected to receive the charge pumped voltage, and a source connected to the fourth detection node; and a fourth inverter having an input terminal connected to the fourth detection node to output the fourth detection signal.

27. The internal voltage generator of claim 1 , wherein the charge-pumped voltage increases linearly with respect to a change in the external power supply voltage before the received external power supply reaches the minimum operation voltage.

28. The internal voltage generator of claim 10 , wherein the charge-pumped voltage increases linearly with respect to a change in the external power supply voltage before the received external power supply reaches the minimum operation voltage.

29. The internal voltage generator of claim 18 , wherein the charge-pumped voltage increases linearly with respect to a change in the external power supply voltage before the received external power supply reaches the minimum operation voltage.