Three-dimensional cascaded power distribution in a semiconductor device

1. An integrated circuit structure, comprising: a plurality of active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer; and a plurality of voltage supply planes, each of the voltage supply planes residing in a respective one of the active layers; wherein the voltage supply planes are configured such that for a given one of the active layers, a voltage supply plane corresponding to the given one of the active layers serves as a virtual ground for another one of the active layers formed above and adjacent to the given active layer.

2. The integrated circuit structure of claim 1 , further comprising a plurality of capacitors, each of the capacitors being connected between a common ground plane in the integrated circuit structure and a respective one of the voltage supply planes.

3. The integrated circuit structure of claim 1 , wherein each of a given one of the voltage supply planes includes at least one capacitor connected between the given voltage supply plane and at least one of the other voltage supply planes.

4. The integrated circuit structure of claim 1 , wherein a voltage supplied to the integrated circuit structure is substantially equal to a sum of voltage requirements corresponding to the respective supply voltage planes.

5. The integrated circuit structure of claim 1 , wherein the voltage supply planes are configured such that leakage current associated with a given one of the active layers is added to current supplied to another of the active layers formed below and adjacent to the given active layer.

6. The integrated circuit structure of claim 1 , further comprising at least one circuit operatively connected between a first one of the voltage supply planes and a second one of the voltage supply planes.

7. The integrated circuit structure of claim 1 , further comprising a plurality of circuits, each of the active semiconductor regions including at least one of the plurality of circuits, the plurality of circuits including at least two timing circuits residing in at least two respective active semiconductor regions, the timing circuits being configured such that a prescribed timing relationship is maintained between the at least two respective active semiconductor layers.

8. The integrated circuit structure of claim 1 , further comprising clock distribution circuitry for distributing a reference clock signal supplied to the integrated circuit structure throughout the integrated circuit structure, the clock distribution circuitry residing in one of the plurality of active layers.

9. The integrated circuit structure of claim 1 , wherein loads on voltage supplies from one active layer to another active layer are substantially balanced so as to facilitate prescribed voltage differentials on each of the voltage supply planes.

10. The integrated circuit structure of claim 1 , further comprising a plurality of circuits, wherein each of the circuits is connected to a corresponding voltage supply plane in such a manner as to achieve uniform power consumption across each of the plurality of active semiconductor regions.

11. The integrated circuit structure of claim 1 , wherein respective capacitances associated with the voltage supply planes are substantially the same.

12. The integrated circuit structure of claim 1 , wherein respective resistances across the active semiconductor layers are substantially the same.

13. The integrated circuit structure of claim 1 , wherein each of the active layers includes corresponding circuitry formed therein, a silicon area of the circuitry in each of the active layers being substantially the same relative to one another such that respective footprints of the active layers are substantially balanced.

14. A method of distributing power in an integrated circuit device, the method comprising the steps of: forming a plurality of active semiconductor regions in a substantially vertical dimension, each active semiconductor region including an active layer; and forming a plurality of voltage supply planes, each of the voltage supply planes being formed in a respective one of the active layers; wherein the voltage supply planes are formed such that for a given one of the active layers, a voltage supply plane corresponding to the given one of the active layers serves as a virtual ground for another one of the active layers formed above and adjacent to the given active layer.

15. The method of claim 14 , further comprising the step of forming a plurality of capacitors in the integrated circuit device, each of the capacitors being connected between a common ground plane in the integrated circuit device and a respective one of the voltage supply planes.

16. The method of claim 14 , further comprising the steps of: forming at least one circuit in each of the active semiconductor regions, the circuits formed in the active semiconductor region including at least two timing circuits formed in at least two respective active semiconductor regions; and configuring the timing circuits such that a prescribed timing relationship is maintained between the corresponding active semiconductor layers in which the at least two timing circuits are formed.

17. The method of claim 14 , further comprising the steps of: forming a plurality of circuits in the integrated circuit device, each of the circuits being connected to a corresponding voltage supply plane; configuring the circuits so as to achieve uniform power consumption across each of the plurality of active semiconductor regions.

18. An integrated circuit structure, comprising: a plurality of active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer; and a plurality of voltage supply planes, each of the voltage supply planes residing in a respective one of the active layers; wherein the voltage supply planes are configured such that leakage current associated with a given one of the active layers is added to current supplied to another of the active layers formed below and adjacent to the given active layer.

19. A method of distributing power in an integrated circuit device, the method comprising the steps of: forming a plurality of active semiconductor regions in a substantially vertical dimension, each active semiconductor region including an active layer; and forming a plurality of voltage supply planes, each of the voltage supply planes being formed in a respective one of the active layers; wherein the voltage supply planes are formed such that leakage current associated with a given one of the active layers is added to current supplied to another of the active layers formed below and adjacent to the given active layer.