Multiple valued dynamic random access memory cell and thereof array using single electron transistor

1. A multi-valued DRAM (dynamic random access memory) cell using a SET (single electron transistor) comprising: a switching transistor to which a data value is transmitted through a bit line BL; a storage capacitor which is connected to a charge storage node to which charges are supplied when the switching transistor is turned on and stores a data value; a load current transistor having a terminal connected to the charge storage node and controlling current supply from a current source to the SET; a voltage control transistor having a terminal connected to the charge storage node so as to be connected to the load current transistor, and the other terminal connected to the SET so as to control a terminal voltage of the SET; the SET having a terminal connected to the voltage control transistor, the other terminal connected to a voltage source terminal, and a gate connected to the charge storage node; and a refresh signal unit which i) is connected to gates of the load current transistor and the voltage control transistor, ii) is enabled by a predetermined period to turn on the transistors, and iii) applies refresh signals for re-charging the storage capacitor.

2. The multi-valued DRAM cell of claim 1 , wherein the switching transistor comprises a first MOS (metal-oxide-semiconductor) transistor M 1 having a terminal connected to the bit line BL and a gate connected to a read word line RWL and a second MOS transistor M 2 having a terminal connected to the other terminal of the first MOS transistor M 1 , the other terminal connected to the charge storage node SN, and a gate connected to a write word line WWL, wherein the load current transistor comprises a fourth MOS transistor M 4 having a terminal connected to the charge storage node SN and a gate applied with a first refresh signal SSG, wherein the voltage control transistor comprises a fifth MOS transistor M 5 having a terminal connected to the charge storage node SN and a gate applied with a second refresh signal SSO, and wherein the multi-valued DRAM cell further comprises a read current transistor composed of a third MOS transistor M 3 which is connected to a common terminal between the first and second MOS transistors M 1 and M 2 and has a gate connected to the charge storage node SN.

3. The multi-valued DRAM cell of claim 2 , wherein the refresh signal unit is connected through a common node to enable the first refresh signal SSG for turning on the load current transistor and the second refresh signal SSO for turning on the voltage control transistor to be simultaneously turned on.

4. The multi-valued DRAM cell of claim 2 , wherein the refresh signal unit is connected to the gates of the load current transistor and the voltage control transistor through different nodes so that the first refresh signal SSG for turning on the load current transistor and the second refresh signal SSO for turning on the voltage control transistor are independently enabled to individually turn on the transistors.

5. The multi-valued DRAM cell of claim 4 , wherein a voltage level applied to the gate of the load current transistor by the first refresh signal SSG and a voltage level applied to the gate of the voltage control transistor by the second refresh signal SSO have different values from each other.

6. The multi-valued DRAM cell of claim 4 , wherein the voltage level applied by the first refresh signal SSG is equal to or larger than the sum of a threshold voltage of the load current transistor and a voltage written to the charge storage node, and wherein the voltage level applied by the second refresh signal SSO is similar to a threshold voltage of the voltage control transistor.

7. The multi-valued DRAM cell of claim 2 , wherein the other terminal of the fourth MOS transistor M 4 is connected to a current source I o .

8. The multi-valued DRAM cell of claim 2 , wherein the other terminal of the third MOS transistor M 3 further comprises a switch for performing a switching operation to a ground voltage or a second voltage source terminal V ss .

9. The multi-valued DRAM cell of claim 8 , wherein the switch is a sixth MOS transistor having a terminal connected to the other terminal of the third MOS transistor M 3 , the other terminal connected to the ground voltage or the second voltage source terminal V ss , and a gate applied with a read auxiliary signal SCEN.

10. The multi-valued DRAM cell of claim 9 , wherein the read auxiliary signal SCEN is enabled only when data written to the multi-valued DRAM cell is read.

11. The multi-valued DRAM cell of claim 2 , wherein the bit line BL is connected to a voltage source for outputting two or more different voltage levels.

12. The multi-valued DRAM cell of claim 2 , wherein periods of the first refresh signal SSG for opening and closing the fourth MOS transistor M 4 and the second refresh signal SSO for opening and closing the fifth MOS transistor M 5 are determined by a time to discharge the storage capacitor.

13. A multi-valued DRAM cell array using a SET, comprising a plurality of multi-valued DRAM cells of claim 2 that are two-dimensionally arrayed, a plurality of bit lines BLO to BL 3 , a plurality of read word lines RWLO to RWL 3 , a plurality of write word lines WWLO to WWL 3 , a plurality of refresh lines SSGO to SSG 3 and SSOO to SS 03 , and a read auxiliary block, wherein each of the multi-valued DRAM cells is connected to a corresponding bit line, a corresponding read word line, a corresponding write word line, and a corresponding refresh line, and the other terminal of the third MOS transistor M 3 is connected to the read auxiliary block, and wherein the read auxiliary block operates in response to a read auxiliary signal SCEN.

14. The multi-valued DRAM cell array of claim 13 , wherein the other terminals of the third MOS transistors M 3 included in the multi-valued DRAM cells arrayed at each of vertical or horizontal lines form a common line to be connected to the read auxiliary block.

15. The multi-valued DRAM cell array of claim 14 , wherein the read auxiliary block has a terminal connected to a second voltage source terminal V ss , the other terminal having a plurality of MOS transistors connected to the common line, and wherein gates of a plurality of the MOS transistors are commonly applied with the read auxiliary signal SCEN.

16. The multi-valued DRAM cell array of claim 15 , wherein the read auxiliary signal SCEN is enabled only when data written to the multi-valued DRAM cell array is read.

17. The multi-valued DRAM cell array of claim 13 , further comprising: a multi-valued DRAM reference cell having the same structure as the multi-valued DRAM cell; and a sense amplifier, wherein the sense amplifier compares a current flowing through the bit line BL connected to the multi-valued DRAM cell with a current flowing through a reference bit line RBL connected to the multi-valued DRAM reference cell.

18. The multi-valued DRAM cell array of claim 17 , wherein the multi-valued DRAM reference cell writes the same voltage value as one of a plurality of different voltage values written to the multi-valued DRAM cell.