The present invention is a phase dithered digital communications system that includes a digital receiver, and uses phase dithering to spread the energy of one or more system clocks to minimize receiver de-sensitization. Phase dithering uses a single frequency for each system clock; however, the energy of each system clock is spread over a range of frequencies by changing the duty-cycle of each clock half-cycle. A non-phase dithered clock drives the sampling clock of a receiver analog-to-digital converter to provide accurate correlation with received information, which may allow use of a higher frequency sampling clock than in frequency dithered designs. Phase dithered clocks and non-phase dithered clocks may have constant frequencies that are related to each other by a ratio of two integers; therefore, the time base used for extracting received data is always correlated and accurate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A communications system comprising: an analog-to-digital converter adapted to: receive an analog down converted receiver signal; provide a digital down converted receiver signal based on the analog down converted receiver signal; and receive a first clock signal comprising a first clock frequency and a plurality of first clock half-cycles, wherein each first clock half-cycle has a duty-cycle that remains essentially constant; digital circuitry adapted to receive a phase-dithered second clock signal comprising a second clock frequency and a plurality of second clock half-cycles, wherein each second clock half-cycle has a duty-cycle that is one of a plurality of duty-cycles, and wherein the second clock frequency has a period that is substantially constant; and clock generator circuitry adapted to provide the first clock signal and the phase-dithered second clock signal.
2. The communications system of claim 1 wherein the phase-dithered second clock signal is used to provide a first system clock for the digital circuitry.
3. The communications system of claim 2 wherein the digital circuitry further comprises a plurality of digital circuits adapted to receive the first system clock such that at least one of the plurality of digital circuits changes state based on the first system clock.
4. The communications system of claim 1 wherein the digital circuitry is further adapted to receive a plurality of clock signals comprising a plurality of clock frequencies, wherein each of the plurality of clock signals comprises a plurality of clock half-cycles, and each clock half-cycle has a duty-cycle that is one of a second group consisting of a plurality of duty-cycles.
5. The communications system of claim 4 wherein the plurality of clock signals is used to provide a plurality of system clocks for the digital circuitry.
6. The communications system of claim 1 wherein the plurality of duty-cycles consists of a short duty-cycle, a nominal duty cycle, and a long duty-cycle.
7. The communications system of claim 1 wherein a ratio of the first clock frequency divided by the second clock frequency is essentially equal to a first integer divided by a second integer.
8. The communications system of claim 1 wherein the digital circuitry is further adapted to receive the digital down converted receiver signal.
9. The communications system of claim 1 wherein the analog down converted receiver signal further comprises an in-phase analog down converted receiver signal and a quadrature-phase analog down converted receiver signal, wherein the in-phase analog down converted receiver signal is phase-shifted from the quadrature-phase analog down converted receiver signal by essentially 90 degrees.
10. The communications system of claim 1 wherein the first clock signal and the second clock signal are based on a reference clock signal.
11. The communications system of claim 1 wherein the duty-cycle of each second clock half-cycle is based on a frequency spreading algorithm.
12. The communications system of claim 1 wherein a pattern for phase-dithering the phase-dithered second clock signal is based on a receive center frequency.
13. The communications system of claim 1 wherein every other second clock half-cycle has a duty-cycle that is a nominal duty-cycle.
14. The communications system of claim 1 wherein the second clock signal further comprises a plurality of second clock cycles, wherein each second clock cycle has a duty-cycle that is one of a plurality of duty-cycles.
15. The communications system of claim 1 wherein the first clock signal is not phase-dithered.
16. The communications system of claim 1 further comprising down conversion circuitry adapted to receive an RF input signal and provide the analog down converted receiver signal.
17. The communications system of claim 1 wherein the analog down converted receiver signal comprises a continuous receiver signal.
18. The communications system of claim 1 wherein the analog down converted receiver signal comprises a wideband code division multiple access (WBCDMA) receiver signal.
19. The communications system of claim 1 wherein the analog down converted receiver signal comprises an enhanced general packet radio service (EGPRS) receiver signal.
20. The communications system of claim 1 further comprising digital receiver circuitry adapted to receive the digital down converted receiver signal, and adapted to receive a third clock signal comprising a third clock frequency and a plurality of third clock half-cycles, wherein each third clock half-cycle has a duty-cycle that remains essentially constant.
21. A method comprising: receiving an analog down converted receiver signal; providing a digital down converted receiver signal based on the analog down converted receiver signal; receiving a first clock signal comprising a first clock frequency and a plurality of first clock half-cycles, wherein each first clock half-cycle has a duty-cycle that remains essentially constant; receiving a phase-dithered second clock signal comprising a second clock frequency and a plurality of second clock half-cycles, wherein each second clock half-cycle has a duty-cycle that is one of a group consisting of a short duty-cycle, a nominal duty cycle, and a long duty-cycle, wherein the period of the second clock frequency is substantially constant; providing the first clock signal to an analog-to-digital converter that is adapted to provide the digital down converted receiver signal; and providing the phase-dithered second clock signal to digital circuitry.
22. A communication system comprising: a frequency synthesizer configured to generate an undithered system clock and a high frequency reference clock; and a phase dithering circuit configured to receive the undithered system clock and the high frequency reference clock, wherein the phase dithering circuit is further configured to generate a phase dithered system clock based upon the undithered system clock and the high frequency reference clock, and wherein the phase dithered system clock has a period that is substantially constant.
23. The communication system of claim 22 further comprising: digital receiver circuitry configured to receive an undithered receiver clock; and digital system circuitry configured to receive the phase dithered system clock.
24. The communication system of claim 22 wherein the phase dithered system clock includes a substantially constant period and the duty-cycle of the phase dithered system clock is phase modulated.
25. The communication system of claim 22 wherein the undithered system clock and the high frequency reference clock are related by a ratio.
26. A method for generating a phase dithered clock comprising: receiving an undithered system clock; receiving a high frequency reference clock; generating a phase dithered system clock based upon the undithered system clock and the high frequency reference clock, and wherein a period of the phase dithered system clock is the same as a period of the undithered system clock; providing the undithered system clock to a digital receiver circuit; and providing the phase dithered system clock to a digital system circuitry.
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April 27, 2007
November 29, 2011
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