Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce thermal crosstalk associated with phase change memory cells, which can provide various benefits including improved data reliability and retention and decreased read and/or write times, among various other benefits. One or more embodiments can reduce the number of processing steps associated with providing local interconnects to phase change memory arrays.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A phase change memory cell, comprising: a stack structure including a phase change material in contact with a first electrode and a second electrode; and a heat sink comprised of a thermally conductive material located between a stack structure associated with an adjacent phase change memory cell; wherein the heat sink is formed over a metal contact coupled to at least one of a source region and a drain region associated with an access transistor corresponding to the phase change memory cell.
2. The memory cell of claim 1 , including a dielectric material formed on a first sidewall of the stack structure and on a first sidewall of the stack structure associated with the adjacent phase change memory cell.
3. The memory cell of claim 2 , wherein the dielectric material is a continuous encapsulation layer formed over the stack structure and the stack structure associated with the adjacent phase change memory cell.
4. The memory cell of claim 3 , wherein the heat sink is located in a gap formed by the continuous encapsulation layer.
5. The memory cell of claim 1 , wherein a thermal conductivity of the thermally conductive material is at least 30 W/m·K.
6. The memory cell of claim 1 , wherein a thermal conductivity of the thermally conductive material is at least 100 W/m·K.
7. The memory cell of claim 1 , wherein the heat sink is comprised of a metal.
8. A phase change memory cell, comprising: a first, a second, and a third metal contact formed on a substrate, the third metal contact located between the first and second metal contact; a first stack structure formed a distance from a second stack structure, the first and the second stack structures including a phase change material in contact with a first electrode and a second electrode, wherein the first electrode of the first stack is coupled to the first metal contact and the first electrode of the second stack is coupled to the second metal contact; a dielectric material formed on a wall of the first and the second stack structure; and a heat sink material formed in a gap between the first stack structure and the second stack structure.
9. The memory cell of claim 8 , wherein the heat sink material is formed over at least a portion of the third metal contact.
10. The memory cell of claim 8 , wherein the first electrode is a bottom electrode and the second electrode is a top electrode.
11. The memory cell of claim 8 , wherein at least one of the first and the second metal contact is a drain contact coupled to a drain region associated with the substrate.
12. The memory cell of claim 8 , wherein the third metal contact is a source contact coupled to a source region associated with the substrate.
13. The memory cell of claim 8 , including a gate of an access transistor formed between the first and the third metal contact.
14. The memory cell of claim 8 , wherein the dielectric material formed on the wall of the first and the second stack structure is also formed over the third metal contact.
15. A phase change memory cell, comprising: a first stack structure formed including a phase change material between a bottom electrode and a top electrode; a first metal contact coupled to the bottom electrode and to an access device corresponding to the memory cell; a heat sink material located between the first stack structure and a second stack structure corresponding to an adjacent phase change memory cell; and a second metal contact coupled to the heat sink material and to the access device corresponding to the memory cell.
16. The memory cell of claim 15 , wherein first metal contact is a drain contact and the second metal contact is a source contact.
17. The memory cell of claim 15 , wherein the heat sink material is coupled to a dielectric material formed on at least a sidewall of the first stack structure and at least a sidewall of the second stack structure.
18. The memory cell of claim 15 , wherein the heat sink material has a thermal conductivity of at least 30 W/m·K.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 9, 2010
December 13, 2011
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