Motion estimation for video compression

1. A method for motion estimation, the method comprising: obtaining a first portion of a predicted frame, the first portion being for a first predicted value; obtaining a first subset of a reference frame, the first subset being for a first reference value; subtracting twice the first predicted value from the first reference value; and multiplying, using an integrated circuit, an outcome of the subtracting by the first reference value to produce a partial result, the partial result for indication of a degree of difference between the first portion and the first subset.

2. The method according to claim 1 , further comprising: the first portion having a first set of first predicted values including the first predicted value, the first set of predicted values being associated with predicted pixel data of the predicted first frame; the first subset having a first set of reference values including the first reference value, the first set of reference values being associated with first reference pixel data of the reference frame; arraying of the first set of predicted values and the first set of reference values relative to one another for the subtracting and the multiplying; and the first set of predicted values and the first set of reference values being arrayed for respectively performing the subtracting and the multiplying to generate a first set of partial results including the partial result.

3. The method according to claim 2 , wherein array pixel dimensions of the first portion and the first subset are equivalent, and wherein the arraying is responsive to array pixel dimension of the first portion.

4. The method according to claim 3 , further comprising: adding the first set of partial results together to produce a first indicator of degree of difference between the first portion and the first subset; and storing the first indicator.

5. The method according to claim 4 , further comprising obtaining a second subset from the reference frame different from the first subset, the second subset having a second set of reference values, the second set of reference values associated with second reference pixel data of the reference frame; repeating the subtracting and the multiplying as arrayed using the first set of predicted values and the second set of reference values; respectively performing the subtracting and the multiplying to generate a second set of partial results using the first set of predicted values and the second set of reference frame values; adding the second set of partial results together to produce a second indicator of degree of difference between the first portion and the second subset; and comparing the second indicator to the first indicator to determine whether the second subset is a closer match to the first portion than the first subset.

6. The method according to claim 5 , further comprising: overwriting the first indicator with the second indicator responsive to the second indicator being less than the first indicator.

7. The method according to claim 3 , wherein the array pixel dimension is for an array selected from a group consisting of a one row and multiple column array, a multiple row and one column array, and a multiple row and multiple column array.

8. The method according to claim 3 , wherein the array pixel dimension is for an array having multiple rows and multiple columns; and the method further comprising: generating carry bits associated with a row of the array; and respectively adding the carry bits with the first set of partial results to produce the first indicator.

9. An integrated circuit, comprising: a digital signal processing block having a subtractor, a multiplier, and an adder; the subtractor coupled to receive a value of a variable B and twice a value of a variable A (“2A”) for providing a result of B−2A; and the multiplier coupled to receive the result of B−2A and to receive the variable B for providing a result of B(B−2A); the variable B being associated with a reference array of pixels, the reference array of pixels being a subset of a reference frame; the variable A being associated with a predicted array of pixels, the predicted array of pixels being a subset of a predicted frame; and the result of B(B−2A) being for motion estimation; wherein the result of B(B−2A) is usable to provide an indication of degree of difference between the variable B and the variable A for determining degree of difference between the subset of the reference frame and the subset of the predicted frame.

10. The integrated circuit according to claim 9 , wherein the adder is coupled to receive the result of B(B−2A) for addition with a carry value C for providing a result of B(B−2A)+C.

11. The integrated circuit according to claim 10 , wherein the carry value C is from a prior stage of digital signal processing with respect to the digital signal processing block.

12. The integrated circuit according to claim 11 , further comprising: a plurality of digital signal processing blocks including the digital signal processing block for providing a respective plurality of results; and an addition stage coupled to receive the plurality of results including the result of B(B−2A)+C; the addition stage configured to add the plurality of results together to provide an indicator of the degree of difference between the reference frame and the predicted frame.

13. The integrated circuit according to claim 12 , wherein the plurality of digital signal processing blocks is a last row in an array of digital signal processing blocks, the array of digital signal processing blocks mapped to provide a motion estimation engine, the motion estimation engine for comparing each of a plurality of subsets of the reference frame including the subset of the reference frame with the subset of the predicted frame using a plurality of respectively associated generated indicators including the indicator.

14. The integrated circuit according to claim 13 , wherein the motion estimation engine is further for comparing each of the plurality of subsets of the reference frame with each of a plurality of subsets of the predicted frame including the subset of the predicted frame, wherein each of the subsets of the predicted frame is accessed one at a time for comparison to each of the plurality of subsets of the reference frame.

15. The integrated circuit according to claim 14 , further comprising: memory coupled to store variables A and B including the variable A and the variable B and configured to output the variable A and the variable B responsive to an input address; a bit shifter coupled to receive the variable A and configured to provide double the value of the variable A; a comparator coupled to respectively receive the indicators for the comparing each one at a time in a sequence; and a storage device coupled to the comparator for storing a compare output associated with a minimum degree of difference and coupled for receiving the input address for association with the compare output stored in the storage device.

16. The integrated circuit according to claim 14 , wherein the addition stage is formed using programmable logic of a programmable logic device; and wherein the comparison is for motion estimation for digital video compression using a modified form of Sum of Square Differences.

17. A method for providing an engine for motion estimation, comprising: determining an array size of an array of pixels, the array of pixels being for predicted data of a predicted frame; associating embedded resources to provide an array of digital signal processing blocks of the array size; configuring each digital signal processing block of the array of digital signal processing blocks to perform a respective portion of an equation B(B−2A), where B is associated with reference data from a reference frame and A is associated with the predicted data from the predicted frame; the array of digital signal processing blocks configured to propagate carry data from respective portions of the equation B(B−2A) and to propagate each output from each respective portion of the equation B(B−2A); a portion of the array of digital signal processing blocks configured to add an associated respective portion of the carry data to an associated respective portion of the equation B(B−2A) from a prior stage of the array of digital signal processing blocks; and programming first programmable resource to provide to receive outputs from a final stage of the array of digital signal processing blocks for summing the outputs to produce a current indicator, the current indicator being associated with a Sum of Square Differences-based result.

18. The method according to claim 17 , further comprising: programming second programmable resource to provide a compare stage for receiving the current indicator and a prior indicator.

19. The method according to claim 18 , further comprising programming third programmable resource to provide a storage stage for receiving a smaller of the current indicator and the prior indicator from the compare stage and to provide the prior indicator stored in the storage stage to the compare stage.

20. The method according to claim 17 , wherein the embedded resources used to provide the array of digital signal processing blocks are of a programmable logic device.