A method of forming a semiconductor structure comprises providing a substrate and forming an insulator layer on the substrate. A first film is formed on the insulator layer. Thus, the first film can correspond to a device region of the semiconductor structure. A second film, comprising a second material that is different from the first material, is also formed on the insulator layer adjacent to the first film. The second material can comprise an isolation material (e.g., an oxide and/or nitride material) and can, for example comprise the same dielectric material as the insulator layer (e.g., silicon dioxide). The second film can correspond to an isolation region (e.g., a shallow trench isolation region) of the semiconductor structure. The second film is specifically formed with a first section having a first thickness and a second section having a second thickness that is different from the first thickness.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a semiconductor structure comprising: providing a substrate; forming, above a first section of said substrate, at least one first device, a first trench isolation region positioned laterally adjacent to said first device, and a plurality of discrete first fill structures adjacent to and in contact with a first top surface of said first trench isolation region and, above a second section of said substrate, at least one second device, a second trench isolation region positioned laterally adjacent to said second device and a plurality of discrete second fill structures adjacent to and in contact with a second top surface of said second trench isolation region, said first section and said second section being in entirely different locations above said substrate, said discrete first fill structures in said first section being formed in a first pattern such that a first amount of an isolation material at said first top surface of said first trench isolation region is exposed, said discrete second fill structures in said second section being formed in a second pattern such that a second amount of said isolation material at said second top surface of said second trench isolation region is exposed, said second pattern being different from said first pattern, said second amount being different from said first amount, and said first amount and said second amount being predetermined so that said first section has first reflectance and absorption characteristics and said second section has second reflectance and absorption characteristics, said first reflectance and absorption characteristics and said second reflectance and absorption characteristics being predetermined based on said first amount and said second amount, respectively, and further being selectively different; and performing a rapid thermal anneal, said first reflectance and absorption characteristics ensuring that a first predetermined maximum temperature is achieved in said first section during said rapid thermal anneal and said second reflectance and absorption characteristics ensuring that a second predetermined maximum temperature is achieved in said second section during said rapid thermal anneal, said first predetermined maximum temperature being different from said second predetermined maximum temperature.
2. The method of claim 1 , said discrete first fill structures being formed so as to comprise at least one of the following: first single crystalline semiconductor structures within said first trench isolation region at said first top surface; first polycrystalline semiconductor structures above and in contact with said first top surface of said first trench isolation region; and first dielectric structures above and in contact with at least a portion of said first top surface of said first trench isolation region; and said discrete second fill structures being formed so as to comprise at least one of the following: second single crystalline semiconductor structures within said second trench isolation region at said second top surface; second polycrystalline semiconductor structures above and in contact with said second top surface of said second trench isolation region; and second dielectric structures above and in contact with at least a portion of said second top surface of said second trench isolation region.
3. The method of claim 2 , said first single crystalline semiconductor structures and said second single crystalline semiconductor structures being formed by forming dummy devices in said first section and said second section.
4. The method of claim 2 , said first polycrystalline semiconductor structures and said second polycrystalline semiconductor structures being formed by forming dummy polysilicon gate structures in said first section and said second section.
5. The method of claim 2 , said first dielectric structures and said second dielectric structures being formed by forming and patterning one of an oxide layer, a nitride layer and an oxide-nitride stack in said first section and said second section.
6. The method of claim 1 , further comprising: prior to said forming, predetermining said first amount of said isolation material to be exposed at said first top surface of said first trench isolation region in said first section and said second amount of said isolation material to be exposed at said second top surface of said second trench isolation region in said second section so that said first device is heated to said first predetermined maximum temperature and said second device is heated to said second predetermined maximum temperature during said rapid thermal anneal.
7. The method of claim 6 , said first predetermined maximum temperature and said second predetermined maximum temperature being different optimal dopant activation temperatures for said first device and said second device.
8. The method of claim 1 , further comprising: prior to said forming, predetermining said first amount of said isolation material to be exposed at said first top surface of said first trench isolation region in said first section and said second amount of said isolation material to be exposed at said second top surface of said second trench isolation region in said second section so that said first device is heated to said first predetermined maximum temperature and said second device is heated to said second predetermined maximum temperature and, as a result, following said rapid thermal anneal, performance characteristics exhibited by said first device and said second device are different.
9. A method of forming a semiconductor structure comprising: providing a substrate; forming, above a first section of said substrate, at least one first device, a first trench isolation region positioned laterally adjacent to said first device, and a plurality of discrete first fill structures adjacent to and in contact with a first top surface of said first trench isolation region and, above a second section of said substrate, at least one second device, a second trench isolation region positioned laterally adjacent to said second device and a plurality of discrete second fill structures adjacent to and in contact with a second top surface of said second trench isolation region, said first section and said second section being in entirely different locations above said substrate; selectively removing at least one discrete fill structure of said discrete first fill structures and said discrete second fill structures so as to achieve a first pattern of said first fill structures in said first section and a second pattern of said second fill structures in said second section, said first pattern ensuring that a first amount of an isolation material at said first top surface of said first trench isolation region is exposed, said second pattern ensuring that a second amount of said isolation material at said second top surface of said second trench isolation region is exposed, said second pattern being different from said first pattern, said second amount being different from said first amount, and said first amount and said second amount being predetermined so that said first section has first reflectance and absorption characteristics and said second section has second reflectance and absorption characteristics, said first reflectance and absorption characteristics and said second reflectance and absorption characteristics being predetermined based on said first amount and said second amount, respectively, and further being selectively different; and performing a rapid thermal anneal, said first reflectance and absorption characteristics ensuring that a first predetermined maximum temperature is achieved in said first section during said rapid thermal anneal and said second reflectance and absorption characteristics ensuring that a second predetermined maximum temperature is achieved in said second section during said rapid thermal anneal, said first predetermined maximum temperature being different from said second predetermined maximum temperature.
10. The method of claim 9 , said discrete first fill structures being formed so as to comprise at least one of the following: first single crystalline semiconductor structures within said first trench isolation region at said first top surface; first polycrystalline semiconductor structures above and in contact with said first top surface of said first trench isolation region; and first dielectric structures above and in contact with at least a portion of said first top surface of said first trench isolation region; and said discrete second fill structures being formed so as to comprise at least one of the following: second single crystalline semiconductor structures within said second trench isolation region at said second top surface; second polycrystalline semiconductor structures above and in contact with said second top surface of said second trench isolation region; and second dielectric structures above and in contact with at least a portion said second top surface of said second trench isolation region.
11. The method of claim 10 , said first single crystalline semiconductor structures and said second single crystalline semiconductor structures being formed by forming dummy devices in said first section and said second section.
12. The method of claim 10 , said first polycrystalline semiconductor structures and said second polycrystalline semiconductor structures being formed by forming dummy polysilicon gate structures in said first section and said second section.
13. The method of claim 10 , said first dielectric structures and said second dielectric structures being formed by forming and patterning one of an oxide layer, a nitride layer and an oxide-nitride stack in said first section and said second section.
14. The method of claim 9 , further comprising: prior to said selectively removing, predetermining said first amount of said isolation material to be exposed at said first top surface of said first trench isolation region in said first section and said second amount of said isolation material to be exposed at said second top surface of said second trench isolation region in said second section so that said first device is heated to said first predetermined maximum temperature and said second device is heated to said second predetermined maximum temperature during said rapid thermal anneal.
15. The method of claim 14 , said first predetermined maximum temperature and said second predetermined maximum temperature being different optimal dopant activation temperatures for said first device and said second device.
16. The method of claim 9 , further comprising: prior to said forming, predetermining said first amount of said isolation material to be exposed at said first top surface of said first trench isolation region in said first section and said second amount of said isolation material to be exposed at said second top surface of said second trench isolation region in said second section so that said first device is heated to said first predetermined maximum temperature and said second device is heated to said second predetermined maximum temperature and, as a result, following said rapid thermal anneal, performance characteristics exhibited by said first device and said second device are different.
17. A method of forming a semiconductor structure comprising: providing a substrate; forming, above a first section of said substrate, at least one first device, a first trench isolation region positioned laterally adjacent to said first device, and a plurality of discrete first fill structures adjacent to and in contact with a first top surface of said first trench isolation region and, above a second section of said substrate, at least one second device, a second trench isolation region positioned laterally adjacent to said second device and a plurality of discrete second fill structures adjacent to and in contact with a second top surface of said second trench isolation region, said first section and said second section being in entirely different locations above said substrate, said first fill structures in said first section being formed in a first pattern such that a first amount of an isolation material at said first top surface of said first trench isolation region is exposed, said second fill structures in said second section being formed in a second pattern such that a second amount of said isolation material at said second top surface of said second trench isolation region is exposed said second pattern being different from said first pattern, said second amount being different from said first amount; performing a rapid thermal anneal; and prior to said forming, predetermining said first amount of said isolation material to be exposed at said first top surface of said first trench isolation region in said first section and said second amount of said isolation material to be exposed at said second top surface of said second trench isolation region in said second section so so that said first section has first reflectance and absorption characteristics and said second section has second reflectance and absorption characteristics that are selectively different from said first reflectance and absorption characteristics, said first reflectance and absorption characteristics ensuring that a first predetermined maximum temperature is achieved in said first section during said rapid thermal anneal and said second reflectance and absorption characteristics ensuring that a second predetermined maximum temperature is achieved in said second section during said rapid thermal anneal, said first predetermined maximum temperature being different from said second predetermined maximum temperature in order to ensure that said first device and said second device exhibit different predetermined performance characteristics following said rapid thermal anneal.
18. The method of claim 17 , said discrete first fill structures being formed so as to comprise at least one of the following: first single crystalline semiconductor structures within said first trench isolation region at said first top surface; first polycrystalline semiconductor structures above and in contact with said first top surface of said first trench isolation region; and first dielectric structures above and in contact with at least a portion of said first top surface of said first trench isolation region; and said discrete second fill structures being formed so as to comprise at least one of the following: second single crystalline semiconductor structures within said second trench isolation region at said second top surface; second polycrystalline semiconductor structures above and in contact with said second top surface of said second trench isolation region; and second dielectric structures above and in contact with at least a portion of said second top surface of said second trench isolation region.
19. The method of claim 18 , said first single crystalline semiconductor structures and said second single crystalline semiconductor structures being formed by forming dummy devices in said first section and said second section.
20. The method of claim 18 , said first polycrystalline semiconductor structures and said second polycrystalline semiconductor structures being formed by forming dummy polysilicon gate structures in said first section and said second section.
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March 8, 2010
December 20, 2011
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