A semiconductor memory device is provided between a refresh request circuit and a command decoder, and includes a refresh synchronous circuit for deactivating a refresh request if an external access request is output from the command decoder. The semiconductor memory device further includes a clock phase adjusting unit that generates a delay to a clock, where the delay is same or longer than the time taken from when the external access request is issued until when a critical path is passed, and the delay is also shorter than one cycle. Then a flip-flop retrieves the request from the command decoder at the clock timing from the clock phase adjusting unit to supply it to the memory cell array.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells for storing data; a refresh request circuit that internally generates a refresh request, the refresh request requesting a refresh operation of the memory cells; a command decoder that receives and decodes an external access request and the refresh request and supplies to the memory cell, the external access request requesting an access to the memory cells from outside; a refresh synchronous circuit that is provided between the refresh request circuit and the command decoder and deactivates the refresh request if the external access request is output from the command decoder; a clock phase adjusting unit that generates a delay to a clock, the delay being same or longer than time taken since the external access request is received until the external access request passes through the command decoder and the refresh request synchronized with the external access request by the refresh synchronous circuit is supplied to the memory cells, and the delay being shorter than one clock cycle; and a flip-flop that is provided between the command decoder and the memory cell array, retrieves the external access request from the command decoder at a clock timing from the clock phase adjusting unit, and supplies to the memory cell array.
2. The semiconductor memory device according to claim 1 , wherein the clock phase adjusting unit comprises a replica circuit of the command decoder.
3. The semiconductor memory device according to claim 2 , wherein the replica circuit further comprises the refresh synchronous circuit.
4. The semiconductor memory device according to claim 1 , wherein the clock phase adjusting unit is composed of a DLL circuit.
5. The semiconductor memory device according to claim 1 , wherein the clock phase adjusting unit is composed of a PLL circuit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 5, 2010
December 20, 2011
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