A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit, comprising: a gate electrode level region including at least two linear-shaped conductive structures formed to extend lengthwise in a first direction, the at least two linear-shaped conductive structures including, a first linear-shaped conductive structure including a portion that forms a gate electrode of a first transistor of a first transistor type, the first linear-shaped conductive structure also including a first extending portion that extends away from a first end of the gate electrode of the first transistor of the first transistor type by a first extension length as measured in the first direction, and a second linear-shaped conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type, the second linear-shaped conductive structure including a first extending portion that extends away from a first end of the gate electrode of the second transistor of the first transistor type by a second extension length as measured in the first direction, wherein the first extension length is different than the second extension length, and wherein the first extension length is larger than a size of the gate electrode of the first transistor of the first transistor type as measured in the first direction.
2. An integrated circuit as recited in claim 1 , wherein the at least two linear-shaped conductive structures further include a third linear-shaped conductive structure including a portion that forms a gate electrode of a first transistor of a second transistor type, the third linear-shaped conductive structure also including a first extending portion that extends away from a first end of the gate electrode of the first transistor of the second transistor type by a third extension length as measured in the first direction, wherein the first and third linear-shaped conductive structures are substantially co-aligned such that the first extending portion of the first linear-shaped conductive structure is separated from the first extending portion of the third linear-shaped conductive structure by a first line end spacing distance as measured in the first direction.
3. An integrated circuit as recited in claim 2 , wherein the gate electrode level region includes at least one linear-shaped conductive structure that does not form a gate electrode of a transistor.
4. An integrated circuit as recited in claim 2 , wherein the first line end spacing distance is less than or equal to 240 nanometers.
5. An integrated circuit as recited in claim 4 , wherein the first line end spacing distance is less than or equal to 160 nanometers.
6. An integrated circuit as recited in claim 2 , wherein the at least two linear-shaped conductive structures further include a fourth linear-shaped conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type, the fourth linear-shaped conductive structure also including a first extending portion that extends away from a first end of the gate electrode of the second transistor of the second transistor type by a fourth extension length as measured in the first direction, wherein the second and fourth linear-shaped conductive structures are substantially co-aligned such that the first extending portion of the second linear-shaped conductive structure is separated from the first extending portion of the fourth linear-shaped conductive structure by a second line end spacing distance as measured in the first direction.
7. An integrated circuit as recited in claim 6 , wherein the gate electrode level region includes at least one linear-shaped conductive structure that does not form a gate electrode of a transistor.
8. An integrated circuit as recited in claim 6 , wherein the first line end spacing distance is substantially equal to the second line end spacing distance.
9. An integrated circuit as recited in claim 8 , wherein each of the first and second line end spacing distances is less than or equal to 240 nanometers.
10. An integrated circuit as recited in claim 9 , wherein each of the first and second line end spacing distances is less than or equal to 160 nanometers.
11. An integrated circuit as recited in claim 1 , further comprising: a substrate region, the gate electrode level region formed above the substrate region; and a first interconnect level region formed above the substrate region, the first interconnect level region including a first linear-shaped conductive interconnect structure formed to extend lengthwise in the first direction.
12. An integrated circuit as recited in claim 11 , wherein the first interconnect level region includes a second linear-shaped conductive interconnect structure formed to extend lengthwise in the first direction, the second linear-shaped conductive interconnect structure positioned next to and spaced apart from the first linear-shaped conductive interconnect structure.
13. An integrated circuit as recited in claim 12 , wherein side-by-side ones of the at least two linear-shaped conductive structures within the gate electrode level region are spaced apart according to a first centerline-to-centerline pitch as measured in a second direction perpendicular to the first direction, and wherein the first and second linear-shaped conductive interconnect structures are positioned in a side-by-side spaced apart manner according to a second centerline-to-centerline pitch as measured in the second direction, the second centerline-to-centerline pitch defined as a fractional multiple of the first centerline-to-centerline pitch.
14. An integrated circuit as recited in claim 13 , wherein the second centerline-to-centerline pitch is less than or equal to the first centerline-to-centerline pitch.
15. An integrated circuit as recited in claim 14 , wherein the fractional multiple of the first centerline-to-centerline pitch is one.
16. An integrated circuit as recited in claim 14 , further comprising: a second interconnect level region formed above the substrate region, the second interconnect level region including a third linear-shaped conductive interconnect structure formed to extend lengthwise in a second direction perpendicular to the first direction.
17. An integrated circuit as recited in claim 16 , wherein the second interconnect level region includes a fourth linear-shaped conductive interconnect structure formed to extend lengthwise in the second direction, the fourth linear-shaped conductive interconnect structure positioned next to and spaced apart from the third linear-shaped conductive interconnect structure.
18. An integrated circuit as recited in claim 1 , further comprising: a substrate region, the gate electrode level region formed above the substrate region; and an interconnect level region formed above the substrate region, the interconnect level region including a first linear-shaped conductive interconnect structure formed to extend lengthwise in a second direction perpendicular to the first direction.
19. An integrated circuit as recited in claim 18 , wherein the interconnect level region includes a second linear-shaped conductive interconnect structure formed to extend lengthwise in the second direction, the second linear-shaped conductive interconnect structure positioned next to and spaced apart from the first linear-shaped conductive interconnect structure.
20. An integrated circuit as recited in claim 1 , wherein side-by-side ones of the at least two linear-shaped conductive structures within the gate electrode level region are spaced apart according to a substantially equal centerline-to-centerline pitch as measured in a second direction perpendicular to the first direction.
21. An integrated circuit as recited in claim 20 , wherein the gate electrode level region includes at least one linear-shaped conductive structure that does not form a gate electrode of a transistor.
22. An integrated circuit as recited in claim 1 , wherein the gate electrode level region includes at least one linear-shaped conductive structure that does not form a gate electrode of a transistor.
23. An integrated circuit as recited in claim 1 , wherein the at least two linear-shaped conductive structures within the gate electrode level region includes a third linear-shaped conductive structure including a portion that forms a gate electrode of a first transistor of a second transistor type, the third linear-shaped conductive structure also including a first extending portion that extends away from a first end of the gate electrode of the first transistor of the second transistor type by a third extension length as measured in the first direction.
24. An integrated circuit as recited in claim 23 , wherein the gate electrode level region includes at least one linear-shaped conductive structure that does not form a gate electrode of a transistor.
25. An integrated circuit as recited in claim 23 , further comprising: a substrate region, the gate electrode level region formed above the substrate region, the substrate region including a central inactive region separating transistors of the first transistor type from transistors of the second transistor type.
26. An integrated circuit as recited in claim 25 , wherein the gate electrode level region includes at least one linear-shaped conductive structure that does not form a gate electrode of a transistor.
27. An integrated circuit as recited in claim 25 , wherein a portion of at least one of the first extending portion of the first linear-shaped conductive structure and the first extending portion of the second linear-shaped conductive structure extends in the first direction past a portion of the first extending portion of the third linear-shaped conductive structure.
28. An integrated circuit as recited in claim 27 , wherein the portion of at least one of the first extending portion of the first linear-shaped conductive structure and the first extending portion of the second linear-shaped conductive structure extends past the portion of the first extending portion of the third linear-shaped conductive structure over the central inactive region.
29. An integrated circuit as recited in claim 28 , wherein the gate electrode level region includes at least one linear-shaped conductive structure that does not form a gate electrode of a transistor.
30. An integrated circuit as recited in claim 1 , further comprising: a plurality of interconnect levels each including a number of conductive interconnect structures, wherein the gate electrode level region includes at least two linear-shaped conductive structures that respectively form gate electrodes of adjacently positioned transistors of a first transistor type that are formed in part by a first shared diffusion region of a first diffusion type, wherein the gate electrode level region includes at least two linear-shaped conductive structures that respectively form gate electrodes of adjacently positioned transistors of a second transistor type that are formed in part by a first shared diffusion region of a second diffusion type, and wherein the first shared diffusion region of the first diffusion type is electrically connected to the first shared diffusion region of the second diffusion type through conductive interconnect structures within at least two interconnect levels of the plurality of interconnect levels.
31. An integrated circuit as recited in claim 30 , wherein the gate electrode level region includes at least one linear-shaped conductive structure that does not form a gate electrode of a transistor.
32. An integrated circuit as recited in claim 30 , wherein the conductive interconnect structures through which the first shared diffusion region of the first diffusion type is electrically connected to the first shared diffusion region of the second diffusion type include a first linear-shaped conductive interconnect structure formed within a first interconnect level.
33. An integrated circuit as recited in claim 32 , wherein the gate electrode level region includes at least one linear-shaped conductive structure that does not form a gate electrode of a transistor.
34. An integrated circuit as recited in claim 33 , wherein each conductive interconnect structure within the first interconnect level through which the first shared diffusion region of the first diffusion type is electrically connected to the first shared diffusion region of the second diffusion type is linear-shaped.
35. An integrated circuit as recited in claim 32 , wherein the conductive interconnect structures through which the first shared diffusion region of the first diffusion type is electrically connected to the first shared diffusion region of the second diffusion type include a second linear-shaped conductive interconnect structure formed within a second interconnect level.
36. An integrated circuit as recited in claim 35 , wherein the gate electrode level region includes at least one linear-shaped conductive structure that does not form a gate electrode of a transistor.
37. An integrated circuit as recited in claim 36 , wherein each conductive interconnect structure within the second interconnect level through which the first shared diffusion region of the first diffusion type is electrically connected to the first shared diffusion region of the second diffusion type is linear-shaped.
38. An integrated circuit as recited in claim 37 , wherein all conductive interconnect structures through which the first shared diffusion region of the first diffusion type is electrically connected to the first shared diffusion region of the second diffusion type is linear-shaped.
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October 1, 2009
January 3, 2012
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