A semiconductor package including a leadframe which has one or more anchor pads formed on and/or defined by the die pad thereof. Such anchor pad(s) may be provided in any one of a multiplicity of different pad shapes, and are adapted to satisfy the required mechanical anchoring and thermal dissipation thresholds for the package, while still enabling high density circuit routing on the printed circuit board under the package. The leadframe of the semiconductor package further includes a plurality of leads which are segregated into at least two sets, with the leads of each set extending along and in spaced relation to respective ones of the peripheral edge segments defined by the die pad. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads of each set by conductive wires. The semiconductor die, the wires, and portions of the die pad and leads are encapsulated by a package body, the bottom surfaces of the anchor pads of the die pad and the bottom surfaces of the leads being exposed in or on a common exterior surface of the package body.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor package comprising: a die pad defining opposed top and bottom pad surfaces, and including at least two anchor pad which protrude from the bottom pad surface and each have a generally quadrangular configuration defining a distal surface, the bottom pad surface being of a first area, and the distal surfaces of the anchor pads having a combined second area which is less than the first area; a plurality of leads which extend at least partially about the die pad in spaced relation thereto; at least one semiconductor die attached to the top pad surface of the die pad and electrically connected to at least one the leads; and a package body defining a generally planar bottom surface, the package body at least partially encapsulating the die pad, the leads and the semiconductor die such that at least the distal surfaces of the anchor pads are exposed in the bottom surface of the package body.
2. The semiconductor package of claim 1 wherein each of the anchor pads is integrally connected to the bottom pad surface.
3. The semiconductor package of claim 1 wherein the die pad has a generally quadrangular configuration defining multiple peripheral edge segments, and the leads are segregated into at least two sets which extend along respective ones of at least two of the peripheral edge segments of the die pad.
4. The semiconductor package of claim 1 wherein the die pad includes four anchor pads protruding from the bottom pad surface in spaced relation to each other, the distal surfaces of the anchor pads having a combined second area which is less than the first area.
5. The semiconductor package of claim 4 wherein the die pad has a generally quadrangular configuration, and the four anchor pads protrude from the bottom pad surface in close proximity to respective ones of four corner regions defined by the die pad.
6. The semiconductor package of claim 1 wherein the semiconductor die is electrically connected to the leads by conductive wires which are covered by the package body.
7. The semiconductor package of claim 1 wherein each of the leads defines opposed top and bottom lead surfaces, and at least portions of the bottom lead surfaces of the leads are exposed in the bottom surface of the package body.
8. The semiconductor package of claim 7 wherein the package body is formed such that portions of the top lead surfaces of the leads are exposed in the package body.
9. The semiconductor package of claim 8 wherein at least portions of the distal surfaces of the anchor pads, the top and bottom lead surfaces of the leads, and the top pad surface of the die pad each include a plating layer disposed thereon.
10. The semiconductor package of claim 7 wherein each of the leads further defines a lead shelf which is recessed relative to the bottom lead surface, disposed in opposed relation to the top lead surface, and extends to an inner end thereof, the lead shelf being covered by the package body.
11. The semiconductor package of claim 1 wherein the die pad further defines a pad shelf which is recessed relative to and circumvents the bottom pad surface, and is disposed in opposed relation to the top pad surface, the pad shelf being covered by the package body.
12. A semiconductor package comprising: a die pad defining opposed top and bottom pad surfaces, and including at least two anchor pads which are disposed on the bottom pad surface and each define a distal surface, the bottom pad surface being of a first area, and the distal surfaces of the anchor pads having a combined second area which is less than the first area; a plurality of leads which each define a bottom lead surface and extend at least partially about the die pad in spaced relation thereto; a semiconductor die attached to the top pad surface of the die pad and electrically connected to at least one the leads; a package body defining a generally planar bottom surface, the package body at least partially encapsulating the die pad, the leads and the semiconductor die such that the distal surfaces of the anchor pads are not covered by the package body, and the bottom pad surface of the die pad and the bottom leads surfaces of the leads are each substantially flush with the bottom surface of the package body; and a solder mask disposed on and covering the bottom pad surface of the die pad.
13. The semiconductor package of claim 12 wherein each of the anchor pads has a generally quadrangular configuration.
14. The semiconductor package of claim 12 wherein the die pad includes four anchor pads disposed on the bottom pad surface in spaced relation to each other, the distal surfaces of the anchor pads having a combined second area which is less than the first area.
15. The semiconductor package of claim 14 wherein the die pad has a generally quadrangular configuration, and the four anchor pads are disposed on the bottom pad surface in close proximity to respective ones of four corner regions defined by the die pad.
16. The semiconductor package of claim 12 wherein each of the leads further defines a top lead surface, and the package body is formed such that at least portions of the top lead surfaces of the leads are exposed in the package body.
17. The semiconductor package of claim 16 wherein each of the leads further defines a lead shelf which is recessed relative to the bottom lead surface, disposed in opposed relation to the top lead surface, and extends to an inner end thereof, the lead shelf being covered by the package body.
18. The semiconductor package of claim 12 wherein the die pad further defines a pad shelf which is recessed relative to and circumvents the bottom pad surface, and is disposed in opposed relation to the top pad surface, the pad shelf being covered by the package body.
19. A semiconductor package comprising: a die pad defining opposed top and bottom pad surfaces, and including at least two anchor pad which protrude from the bottom pad surface and each define a distal surface, the bottom pad surface being of a first area, and the distal surfaces of the anchor pads having a combined second area which is less than the first area, the die pad further defining a pad shelf which is recessed relative to and circumvents the bottom pad surface, and is disposed in opposed relation to the top pad surface; a plurality of leads which extend at least partially about the die pad in spaced relation thereto; at least one semiconductor die attached to the top pad surface of the die pad and electrically connected to at least one the leads; and a package body defining a generally planar bottom surface, the package body at least partially encapsulating the die pad, the leads and the semiconductor die such that at least the distal surfaces of the anchor pads are exposed in the bottom surface of the package body and the pad shelf is covered thereby.
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January 25, 2010
January 3, 2012
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