An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives a plurality of IQ receiver streams and forms a single stream for use by a packet detector, which is controllable by an SNR_MODE indicating whether the signal to noise ratio is above or below a particular threshold, and a PD_RESET signal indicating that no packet detection should occur. The controller also receives a PACKET_DET signal indicating that packet detection is completed. The packet detection controller examines the incoming receiver streams and suspends AGC process if a packet detect is generated, or suspends the packet detector if an AGC process is required.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A process for a packet detection controller in an initial interpacket mode, said packet detection controller examining each of a plurality of RX_IQ streams of baseband data and asserting an associated GT_NFLR when an increase in signal level on a particular said stream exceeds a noise floor by an increment delta which is associated with said stream, each said stream generated by an antenna coupled to a variable gain amplifier coupled to a mixer forming said stream, said variable gain for each said stream controlled by an associated AGC controller, said streams equally weighted and applied to a packet detector with an SNR_MODE input initially set to LOW, the packet detector asserting a PACKET_DET output when a packet is detected, said packet detector also having a PD_RESET input for suspending the packet detection response of said packet detector; the process comprising: a first step of examining said plurality of said RX_IQ streams and if at least one said GT_NFLR is asserted before said PACKET_DET, asserting said SNR_MODE input to HIGH, asserting said PD_RESET input for a duration of time equal to an AGC process time during which time said AGC controller adjusts the gain of each said variable gain amplifier, thereafter unasserting said PD_RESET until said PACKET_DET is asserted within an interval of time following said GT_NFLR assertion, and if said PACKET_DET is not asserted within an interval after said GT_NFLR assertion, asserting said SNR_MODE signal to LOW and resetting said AGC controllers to an initial state; a second step of performing a single step AGC correction and suspending said AGC process if said PACKET_DET is asserted before the assertion of any said GT_NFLR signal.
2. The process of claim 1 where said packet detector includes a correlator which correlates said input stream with a delayed and conjugated copy of said input stream.
3. The process of claim 1 where said packet detector includes an accumulator which averages a greater number of samples when said SNR_MODE is LOW than when said SNR_MODE is HIGH.
4. The process of claim 1 where said GT_NFLR is asserted for a particular stream if said stream increases by an associated delta above a noise floor.
5. The process of claim 1 where said GT_NFLR is asserted for a particular stream if said stream increases by at least 10 dB above a noise floor.
6. The process of claim 1 where a timer is started upon the assertion of said at least one GT_NFLR, and if said PACKET_DET is not asserted upon expiration of said timer, the gain value for the stream associated with said timer is decreased.
7. The process of claim 1 where a gain value for a particular stream is increased after a successful packet reception.
8. The process of claim 1 where said AGC controller generates at least one gain control signal with an initial value, said gain controller includes a process whereby upon detection of an increased signal level, said AGC controller asserts an associated said GT_NFLR and after the completion of said AGC process asserts a signal AGC_LOCK.
9. The process of claim 8 where said AGC controller suspends said AGC process upon the assertion of said PACKET_DET.
10. The process of claim 1 where each said AGC controller performs a one-shot AGC adjustment if said SNR_MODE is low and said PACKET_DET is asserted.
11. The process of claim 1 where after said SNR_MODE is asserted HIGH, said AGC process comprises said AGC controller performing multi-step AGC correction on each said RX_IQ stream.
12. The process of claim 1 where said delta is 15 dB.
13. A process for packet detection and AGC control, the process having the steps: an IQ stream generation step where a single stream of IQ data is formed from weighted RX_IQ streams, each said RX_IQ stream is formed from the output of a baseband digitizer coupled to a mixer, the mixer coupled to a variable gain amplifier, the variable gain amplifier coupled to an antenna receiving wireless packets, said variable gain amplifier having a gain controlled by an AGC controller; a packet detector step where said packet detector examines said single stream of IQ data and asserts a PACKET_DET output upon detection of a packet in said single stream of IQ data, said packet detector also having a PD_RESET input for suspending said detection of a packet; said packet detector having a sensitivity controlled by an SNR_MODE input; a signal level comparison step operative for each said RX_IQ stream, said signal level comparison step asserting a GT_NFLR signal when an associated said RX_IQ stream has a signal level which is greater than a noise floor by a signal threshold; a packet detector reset step where if at least one said GT_NFLR signal is asserted, said PD_RESET input is asserted for the duration of an AGC process, and also asserting said SNR_MODE signal to HIGH; otherwise if no said GT_NFLR signal is asserted, not asserting said PD_RESET and asserting said SNR_MODE to LOW; an AGC freeze step for causing said AGC process to perform a one-step AGC adjustment if said SNR_MODE signal is LOW upon the assertion of said PACKET_DET, thereafter suspending said AGC process and using a previously derived gain control value.
14. The process of claim 13 where said stream weighting is equal for all said RX_IQ streams.
15. The process of claim 13 where said packet detector step has a timer which causes said AGC process to reset if packet detection is not achieved within a packet duration.
16. The process of claim 13 where said AGC process performs a multi-step AGC adjustment when said SNR_MODE is HIGH, and said PD_RESET is asserted until said multi-step AGC adjustment is completed.
17. The process of claim 13 where said signal threshold is 10dB or more.
18. The process of claim 13 where said freezing said AGC process results in each AGC controller for each stream having performing a single AGC gain adjustment step to a stream gain value and preserving said stream gain value until PACKET_DET is no longer asserted.
19. The process of claim 13 where said packet detector includes an accumulator which averages a greater number of samples when said SNR_MODE is LOW than when said SNR_MODE is HIGH.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 16, 2008
January 3, 2012
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