Semiconductor structure and method of forming the same

1. A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has a first area and a second area; sequentially forming a dielectric layer and a metal layer over the substrate in the first area and the second area; removing the metal layer in the first area by using a salicide block mask; forming a polysilicon layer over the substrate in the first area and the second area; patterning the polysilicon layer and the dielectric layer to form a resistor in the first area and patterning the polysilicon layer, the metal layer and the dielectric layer to form a metal gate structure in the second area; and forming a salicide block layer over the substrate and then removing a portion of the salicide block layer from the second area to expose the polysilicon layer and the substrate in the second area.

2. The method of claim 1 , further comprising forming a shallow trench isolation structure in the substrate in the first area.

3. The method of claim 1 , wherein during the step of removing the metal layer in the first area comprises: forming a patterned photoresist layer over the substrate to expose the metal layer in the first area, wherein a mask used for forming the patterned photoresist layer is the salicide block mask used for forming the salicide block layer; and removing the metal layer in the first area by using the patterned photoresist layer as a mask.

4. The method of claim 1 , wherein the patterned photoresist layer comprises a negative photoresist material.

5. The method of claim 1 , wherein the dielectric layer is a stacked structure comprising a high-k layer and a cap layer sequentially formed on the substrate.

6. The method of claim 5 , wherein the high-k layer comprises HfO 2 , ZrO 2 , Al 2 O 3 , AlN, TiO 2 , La 2 O 3 , Y 2 O 3 , Gd 2 O 3 , Ta 2 O 5 or a combination thereof.

7. The method of claim 5 , wherein the cap layer comprises Al 2 O 3 , Ga 2 O 3 , In 2 O 3 or Ti 2 O 3 when the second area is for forming a PMOS transistor, or comprises La 2 O 3 , Dy 2 O 3 , Y 2 O 3 , MgO 2 or an oxide of a lanthanide series element when the second area is for forming a NMOS transistor.

8. The method of claim 1 , wherein the metal layer comprises TiN, TaC, TaCNO, TaCN or TaN.

9. A semiconductor structure, comprising: a substrate, having a first area and a second area; a resistor, disposed in the first area, wherein the resistor does not comprise any metal layer, wherein a shallow trench isolation structure is disposed in the substrate in the first area below the resistor, and wherein a salicide block layer is disposed in the first area covering the resistor; and a metal gate structure, disposed in the second area, wherein the resistor and the metal gate structure are in substantially the same plane, wherein the resistor comprises a dielectric layer and a polysilicon layer sequentially disposed on the substrate, wherein the dielectric layer is a stacked structure comprising a high-k layer and a cap layer sequentially disposed on the substrate, and wherein the high-k layer comprises HfO 2 , ZrO 2 , Al 2 O 3 , AlN, TiO2, La 2 O 3 , Y 2 O 3 , Gd 2 O 3 , Ta 2 O 5 or a combination thereof; and wherein the cap layer comprises Al 2 O 3 , Ga 2 O 3 , In 2 O 3 or Ti 2 O 3 when the second area is for forming a PMOS transistor, or comprises La 2 O 3 , Dy 2 O 3 , Y 2 O 3 , MgO 2 or an oxide of a lanthanide series element when the second area is for forming a NMOS transistor.

10. The semiconductor structure of claim 9 , wherein the metal gate structure comprises a dielectric layer, a metal layer and a polysilicon layer sequentially disposed on the substrate.

11. The semiconductor structure of claim 10 , wherein the metal layer comprises TiN, TaC, TaCNO, TaCN or TaN.

12. A semiconductor structure, comprising: a substrate, having a first area and a second area; a resistor, disposed in the first area and comprising a first insulation layer, a first high-k layer, a first cap layer and a first polysilicon layer sequentially disposed on the substrate in the first area, wherein the resistor does not comprise any metal layer, and wherein a shallow trench isolation structure is disposed in the substrate in the first area below the resistor; and a metal gate structure, disposed in the second area and comprising a second insulation layer, a second high-k layer, a second cap layer, a metal layer, a second polysilicon layer and a metal salicide layer sequentially disposed on the substrate in the second area.