In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An operation method for a memory including a plurality of memory cells, comprising steps of: performing a first reading operation on the memory cells by applying a reference voltage; checking if a first total number of a first logic state in the first reading operation is correct or not; moving the reference voltage if the first total number of the first logic state in the first reading operation is not correct; performing a second reading operation on the memory cells by applying the moved reference voltage; checking if a second total number of the first logic state in the second reading operation is correct or not; comparing the first total number of the first logic state in the first reading operation with the second total number of the first logic state in the second reading operation if the second total number of the first logic state in the second reading operation is not correct; and stopping the moving the reference voltage step if the first total number of the first logic state in the first reading operation is the same as the second total number of the first logic state in the second reading operation, and storing the moved reference voltage as a target reference voltage.
2. The operation method according to claim 1 , wherein the step of moving the reference voltage if the first total number of the first logic state in the first reading operation is not correct comprises: moving down the reference voltage if the first total number of the first logic state in the first reading operation is more than a total number of the first logic state in an original data; and moving up the reference voltage if the first total number of the first logic state in the first reading operation is fewer than the total number of the first logic state in the original data.
3. The operation method according to claim 1 , further comprising: moving the reference voltage up or down if the first total number of the first logic state in the first reading operation is different from the second total number of the first logic state in the second reading operation.
4. The operation method according to claim 1 , further comprising: if data read in the first reading operation and in the second reading operation are both error, it is determined that there are defect bits in the memory cells if the first total number of the first logic state in the first reading operation is the same as the second total number of the first logic state in the second reading operation; and covering the defect bits in the memory cells by error correction.
5. The operation method according to claim 1 , wherein: the memory cells are multi-level cells and the reference voltage is a level 2 word line reference voltage, a level 3 word line reference voltage or a level 1 word line reference voltage.
6. The operation method according to claim 1 , wherein the memory including a plurality of pages each including a plurality of memory cells, the operation method further comprising: setting respective initial reference voltage for other pages as the target reference voltage for a page of the same page.
7. The operation method according to claim 6 , wherein: the memory cells are multi-level cells; and the reference voltage is a level 2 word line reference voltage, a level 3 word line reference voltage or a level 1 word line reference voltage.
8. A memory including: a memory array including a plurality of memory cells; and a read control circuit, coupled to the memory array, the read control circuit controlling reading operation on the memory array; wherein in a first reading operation, the memory cells are read by applying a reference voltage; the read control circuit checks if a first total number of a first logic state in the first reading operation is correct or not; the read control circuit moves the reference voltage if the first total number of the first logic state in the first reading operation is not correct; in a second reading operation, the memory cells are read by applying the moved reference voltage; the read control circuit checks if a second total number of the first logic state in the second reading operation is correct or not; the read control circuit compares the first total number of the first logic state in the first reading operation with the second total number of the first logic state in the second reading operation if the second total number of the first logic state in the second reading operation is not correct; and the read control circuit stops movement of the reference voltage if the first total number of the first logic state in the first reading operation is the same as the second total number of the first logic state in the second reading operation, and stores the moved reference voltage as a target reference voltage.
9. The memory according to claim 8 , wherein: the read control circuit moves down the reference voltage if the first total number of the first logic state in the first reading operation is more than a total number of the first logic state in an original data; and the read control circuit moves up the reference voltage if the first total number of the first logic state in the first reading operation is fewer than the total number of the first logic state in the original data.
10. The memory according to claim 8 , wherein: the read control circuit moves the reference voltage up or down if the first total number of the first logic state in the first reading operation is different from the second total number of the first logic state in the second reading operation.
11. The memory according to claim 8 , wherein: if data read in the first reading operation and in the second reading operation are both error, the read control circuit determines that there are defect bits in the memory cells if the first total number of the first logic state in the first reading operation is the same as the second total number of the first logic state in the second reading operation; and the read control circuit covers the defect bits in the memory cells by error correction.
12. The memory according to claim 8 , wherein: the memory cells are multi-level cells and the reference voltage is a level 2 word line reference voltage, a level 3 word line reference voltage or a level 1 word line reference voltage.
13. The memory according to claim 8 , wherein: the memory array includes a plurality of pages each including a plurality of memory cells; and the read control circuit sets respective initial reference voltage for other pages as the target reference voltage for a page of the same page.
14. The memory according to claim 13 , wherein: the memory cells are multi-level cells; and the reference voltage is a level 2 word line reference voltage, a level 3 word line reference voltage or a level 1 word line reference voltage.
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October 9, 2009
January 10, 2012
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