In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: a buffer to receive and store packet data, the packet data received from a single channel of packet data; two or more thresholds defined for the buffer, each threshold defining a respective amount of storage space for the buffer; a plurality of processors to process the packet data stored in the buffer, each of the plurality of processors associated with a different one of the thresholds; and a processor control module, the processor control module capable of activating one of the plurality of processors when one of the corresponding thresholds is exceeded to process the packet data from the buffer.
2. The apparatus as described in claim 1 , further comprising an additional processor that is not associated with one of the thresholds.
3. The apparatus as described in claim 2 , wherein a number of processors is not equal to a number of the two or more thresholds.
4. The apparatus as described in claim 1 , wherein the processor control module is capable of deactivating one or more of the plurality of processors when the amount of packet data stored in the buffer becomes less than a corresponding said threshold.
5. The apparatus as described in claim 1 , wherein the processor control module is capable of activating at least two of the plurality of processors when two of the corresponding thresholds are exceeded.
6. The apparatus as described in claim 1 , wherein the buffer is configured as a first in/first out (FIFO) buffer.
7. The apparatus as described in claim 1 , wherein the buffer is a logical buffer that includes a plurality of buffer devices.
8. The apparatus as described in claim 1 , further comprising an additional processor designated as a parent such that it is not activated or deactivated based on the two or more thresholds; and wherein the plurality of processors are designated as children such that they are activated or deactivated based on the corresponding thresholds.
9. The apparatus as described in claim 1 , wherein: at least one of the plurality of processors is associated with a clock control module that is configured to control operation of a clock of the processor; and the processor control module activates the one of the plurality of processors using the clock control module.
10. The apparatus as described in claim 1 , wherein the buffer, the plurality of processors and the processor control module are formed on a single integrated circuit.
11. A method comprising: determining, by a processor control module, that an amount of packet data stored in a buffer exceeds one of two or more thresholds defined for the buffer, the packet data received from a single channel of packet data, each of the thresholds defining a respective amount of data storage space for the buffer; and managing, by the processor control module, how many of a plurality of processors are to be used to process the packet data from the buffer by activating one of the plurality of processors that corresponds to the threshold.
12. The method as described in claim 11 , wherein an additional processor used to process packet data from the buffer does not correspond to one of the thresholds.
13. The method as described in claim 11 , wherein: the buffer is configured as a first in/first out (FIFO) buffer; and the packet data is stored in the buffer as a plurality of data packets or as fragments of data packets.
14. The method as described in claim 11 , wherein the buffer is a logical buffer that includes a plurality of buffer devices.
15. The method as described in claim 11 , wherein: an additional processor is designated as a parent such that it is not activated or deactivated based on the two or more thresholds; and the plurality of processors are designated as children such that they are activated or deactivated based on the corresponding thresholds.
16. The method as described in claim 11 , wherein: at least one said processor is associated with a clock control module that is configured to control operation of a clock of the processor; and the managing is performed, at least in part, using the clock control module.
17. The method as described in claim 11 , wherein the buffer, the plurality of processors and the processor control module are formed on a single integrated circuit.
18. A method comprising: determining that one of two or more thresholds of a buffer is exceeded by an amount of packet data stored by the buffer, each of the thresholds defining a respective amount of storage space of the buffer, the packet data received from a single channel of packet data; and responsive to the determining, causing a processor control module to activate an additional processor associated with the exceeded threshold to process at least a portion of the packet data that exceeds the exceeded threshold.
19. The method as described in claim 18 , wherein the buffer, the additional processor and the processor control module are formed on a single integrated circuit.
20. The method as described in claim 18 , wherein the threshold defines a particular amount of storage space of the buffer that is less than a total amount of storage space of the buffer that is available to store packet data.
21. The method as described in claim 18 , wherein the buffer is a logical buffer that is formed using a plurality of buffer devices.
22. The method as described in claim 18 , wherein the activating is performed using a clock control module that is configured to enable one or more clocks for the one or more additional processors.
23. The method as described in claim 18 , further comprising causing the processor control module to deactivate the additional processor when the amount of packet data stored by the buffer does not exceed the threshold.
24. A system comprising: means for buffering packet data received from a single channel of packet data, the buffering means having two or more thresholds each defining a respective amount of storage space for the buffering means; a plurality of means for processing the packet data, each being communicatively coupled to the buffering means and associated with a different one of the thresholds; and means for activating one of the plurality of processing means when one of the corresponding thresholds is exceeded to process the packet data from the buffering means.
25. The system as described in claim 24 , further comprising means for deactivating one of the plurality of processing means when the corresponding threshold is no longer exceeded.
26. The system as described in claim 24 , wherein: an additional processing means is designated as a parent such that it is not activated or deactivated based on the two or more thresholds; and the plurality of processor means are designated as children such that they are activated or deactivated based on the corresponding thresholds.
27. The system as described in claim 24 , wherein: at least one of the plurality of processing means is associated with means for controlling operation of a clock of the processing means; and the activating means is to manage the plurality of processing means to process the packet data using the controlling means.
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April 4, 2008
January 10, 2012
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