A method and system for a tiling bias design for an integrated circuit device to facilitate efficient design rule checking. The method is implemented in a computer implemented design synthesis system. The method includes receiving a circuit netlist, wherein the circuit netlist represents an integrated circuit design to be realized in physical form. A deep N-well bias voltage distribution structure is provided within the circuit netlist, wherein the structure includes a plurality of tiles arranged to distribute a bias voltage to a plurality of N-wells of the circuit netlist.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method, comprising: receiving a circuit netlist at a computer, wherein the circuit netlist represents an integrated circuit design to be realized in physical form; and including a deep N-well bias voltage distribution structure within the circuit netlist by using the computer, wherein the structure comprises a plurality of tiles arranged to distribute a bias voltage to a plurality of N-wells of the circuit netlist, and wherein a size of at least one tile is dependent on a desired size of a bounding box of a design rule checking process.
2. The method of claim 1 , wherein the plurality of tiles are arranged in an orthogonal grid with respect to a plurality of components of the circuit netlist.
3. The method of claim 2 , wherein the orthogonal grid of the plurality of tiles is arranged in a repeatable modular pattern with respect to the components of the circuit netlist.
4. The method of claim 1 , wherein the plurality of tiles are sized to facilitate operation of the design rule checking process.
5. The method of claim 1 , wherein the plurality of tiles are less than 5 times a size of a design rule checking constraint for the circuit netlist.
6. The method of claim 1 , wherein the plurality of tiles are at least one of a diagonal tile, column tile, row tile, column screen tile, or diagonal screen tile.
7. An integrated circuit device, comprising: an integrated circuit die including a plurality of circuit components fabricated thereon; and a deep N-well bias voltage distribution structure within the integrated circuit die, wherein the structure comprises a plurality of tiles arranged to distribute a bias voltage to a plurality of N-wells of the integrated circuit die, and wherein a size of at least one tile is dependent on a desired size of a bounding box of a design rule checking process.
8. The integrated circuit device of claim 7 , wherein the plurality of tiles are arranged in an orthogonal grid with respect to the components of the integrated circuit die.
9. The integrated circuit device of claim 8 , wherein the orthogonal grid of the plurality of tiles is arranged in a repeatable modular pattern with respect to the components of the integrated circuit die.
10. The integrated circuit device of claim 7 , wherein the plurality of tiles are sized to facilitate operation of the design rule checking process.
11. The integrated circuit device of claim 7 , wherein the plurality of tiles are less than 5 times a size of a design rule checking constraint for the integrated circuit die.
12. The integrated circuit device of claim 7 , wherein the plurality of tiles are at least one of a diagonal tile, column tile, row tile, column screen tile, or diagonal screen tile.
13. A tangible computer-readable storage device having instructions stored thereon, the instructions comprising: instructions for receiving a circuit netlist, wherein the circuit netlist represents an integrated circuit design to be realized in physical form; and instructions for including a deep N-well bias voltage distribution structure within the circuit netlist, wherein the structure comprises a plurality of tiles arranged to distribute a bias voltage to a plurality of N-wells of the circuit netlist, and wherein a size of at least one tile is dependent on a desired size of a bounding box of a design rule checking process.
14. The tangible computer-readable storage device of claim 13 , wherein the plurality of tiles are arranged in an orthogonal grid with respect to a plurality of components of the circuit netlist.
15. The tangible computer-readable storage device of claim 14 , wherein the orthogonal grid of the plurality of tiles is arranged in a repeatable modular pattern with respect to the components of the circuit netlist.
16. The tangible computer-readable storage device of claim 13 , wherein the plurality of tiles are sized to facilitate operation of the design rule checking process.
17. The tangible computer-readable storage device of claim 13 , wherein the plurality of tiles are less than 5 times a size of a design rule checking constraint for the circuit netlist.
18. The tangible computer-readable storage device of claim 13 , wherein the plurality of tiles are at least one of a diagonal tile, column tile, row tile, column screen tile, or diagonal screen tile.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 20, 2007
January 17, 2012
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