A displacement detection pattern, usable for detection of a relative displacement between a wiring and a via plug, includes a wiring provided between via plugs and a conductor. The conductor is provided in the same layer level as a level at which the wiring is provided and is provided at a predetermined distance from the wiring.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A displacement detection pattern, comprising: a first via plug formed at a first layer level; a second via plug formed at said first layer level; a first wiring formed on said first via plug at a second layer level; a second wiring formed on said second via plug at said second layer level; a third via plug formed on said first wiring; a fourth via plug formed on said second wiring; a first conductor connected to said first and second via plugs; and a second conductor formed at said second layer level to surround said first and second wirings.
2. The displacement detection pattern as claimed in claim 1 , wherein an area of said third via plug facing said first wiring is smaller than an area of said first wiring.
3. The displacement detection pattern as claimed in claim 1 , wherein an area of said first wiring facing said third via plug is smaller than an area of said third via plug.
4. A semiconductor device comprising a displacement detection pattern, wherein said displacement detection pattern comprises: a first via plug formed at a first layer level; a second via plug formed at said first layer level; a first wiring formed on said first via plug at a second layer level; a second wiring formed on said second via plug at said second layer level; a third via plug formed on said first wiring; a fourth via plug formed on said second wiring; a first conductor connected to said first and second via plugs; and a second conductor formed at said second layer level to surround said first and second wirings.
5. The semiconductor device as claimed in claim 4 , wherein an area of said third via plug facing said first wiring is smaller than an area of said first wiring.
6. The semiconductor device as claimed in claim 4 , wherein an area of said first wiring facing said third via plug is smaller than an area of said third via plug.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 8, 2008
January 24, 2012
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