An integrated circuit may include multiple programmable metallization cells (PMCs) and a multiple bit lines. Each bit line may be connected to a anodes of a different set of PMCs, and provide a read data path from a selected one of the set of PMCs. Access devices may each provide a controllable impedance path between at least one cathode and a common source node.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit, comprising: a plurality of programmable metallization cells (PMCs) each comprising an ion conducting material and an active metal dissolvable in the ion conducting material and each having a cathode and an anode comprising the active metal; a plurality of bit lines, each bit line coupled to a plurality of anodes of a different set of PMCs, and providing a read data path from a selected one of the set of PMCs; a plurality of access devices that each provide a controllable impedance path between at least one cathode and a common source node; and de-select circuitry that drives the bit line and corresponding common source node of a de-selected PMC cell to a same potential.
2. The integrated circuit of claim 1 , further including: source driving circuitry that selectively couples the common source node between at least a first power supply node or a second power supply node in response to a mode signal.
3. The integrated circuit of claim 1 , further including: bit line switching circuits that each selectively couple a corresponding bit line to a first power supply node or a second power supply node in response to a bit line select signal.
4. The integrated circuit of claim 3 , further including: each bit line switching circuit couples the corresponding bit line to the first power supply node in response to at least address information and a mode value that indicates a program operation, and couples the corresponding bit line to the second power supply node in response to at least the mode value indicating an erase operation; and source driving circuitry that couples the common source node to the second power supply node in response to at least address information and the mode value indicating the program operation, and couples the common source node to the first power supply node in response to at least the mode value indicating the erase operation.
5. The integrated circuit of claim 1 , wherein: the de-select circuitry electrically isolates each bit line and corresponding PMC cells and access devices when the bit line is de-selected from an operation.
6. The integrated circuit of claim 1 , wherein: the access devices each comprise a transistor formed in a substrate that includes a first diffusion region; and the common source node comprises the first diffusion regions and a strap metallization that conductively connects the first diffusion regions to one another.
7. The integrated circuit device of claim 1 , further including: the bit lines are disposed in a first direction; a plurality of word lines connected to access devices disposed in a second direction, different from the first direction; and the common source node comprises a strap metallization disposed in the first direction that conductively connects first diffusion regions of a group of access devices to one another.
8. The integrated circuit device of claim 7 , further including: the first diffusion regions are integral regions, each integral region forming a portion of no less than four access devices.
9. The integrated circuit device of claim 1 , wherein: each bit line and the plurality of anodes for such bit line are an integral structure.
10. The integrated circuit device of claim 1 , wherein: each bit line is an integral structure separate from the plurality of anodes for the bit line.
11. An integrated circuit, comprising: a plurality of programmable metallization cells (PMCs) having an anode terminal comprising a metal dissolvable into an ion conducting material and programmable between at least two different impedance states, and having cathodes connected to a corresponding access device; a plurality of bit lines arranged in a first direction, each bit line in contact with a different group PMCs and comprising at least one conductive layer separate from the anode terminals of its group of PMCs; and a plurality of source strap lines arranged in the first direction, each source strap line in contact with a different group of access devices, each access device sharing a semiconductor region with a plurality of other access devices.
12. The integrated circuit of claim 11 , wherein: each source strap line comprises a metallization line commonly connected to at least one shared semiconductor region.
13. The integrated circuit of claim 11 , further including: each access device comprises an access transistor that enables a controllable impedance path in response to a signal at a control terminal; and a plurality of word lines arranged in a second direction different from the first direction, each word line conductively connected to the control terminals of a plurality of access devices.
14. The integrated circuit of claim 13 , wherein: each word line comprises an integral conductive line formed over a plurality of access transistors.
15. The integrated circuit of claim 11 , further including: a bit line select circuit that selectively connects a subset of the bit lines to selected bit line voltages in response to address data; and a source select circuit that selectively connects a subset of the source strap lines to selected source line voltage in response to address data.
16. An integrated circuit, comprising: a plurality of programmable metallization cells (PMCs) each comprising an ion conducting material and an active metal dissolvable in the ion conducting material and each having a cathode and an anode comprising the active metal; a plurality of bit lines, each bit line coupled to a plurality of anodes of a different set of PMCs, and providing a read data path from a selected one of the set of PMCs; and a plurality of access devices that each provides a controllable impedance path between the cathodes of the PMCs and a plurality of source nodes; and source driving circuitry that selectively couples the source nodes between at least two different nodes in response to at least a mode signal and in response to address information.
17. The integrated circuit of claim 16 , further including: bit line switching circuits that selectively couple the bit lines between at least two different nodes in response to at least address information.
18. An integrated circuit, comprising: a plurality of programmable metallization cells (PMCs), each having an anode terminal comprising a metal dissolvable into an ion conducting material and a cathode terminal connected to a corresponding access device; a plurality of bit lines arranged in a first direction, each bit line in contact with a different group of PMCs and having at least one conductive layer that includes the anode terminals of its group of PMCs; and a plurality of source strap contact with a different group of access devices, each access device sharing a semiconductor region with a plurality of other access devices.
19. The integrated circuit of claim 18 , wherein: each source strap line comprises a metallization line commonly connected to at least one shared semiconductor region.
20. The integrated circuit of claim 18 , further including: each access device comprises an access transistor that enables a controllable impedance path in response to a signal at a control terminal; and a plurality of word lines arranged in a second direction different from the first direction, each word line conductively connected to the control terminals of a plurality of access devices.
21. The integrated circuit of claim 20 , wherein: each word line comprises an integral conductive line formed over a plurality of access transistors.
22. The integrated circuit of claim 18 , further including: a bit line select circuit that selectively connects a subset of the bit lines to selected bit line voltages in response to address data; and a source select circuit that selectively connects a subset of the source strap lines to selected source line voltage in response to address data.
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July 23, 2009
January 31, 2012
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