A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A processing system, comprising: a receiving device; a bus having an address channel, a write channel, and a read channel; and a sending device configured to send an address to the receiving device on the address channel and to receive read data from the receiving device on the read channel, the sending device being further configured to concurrently send a portion of a payload to the receiving device on the write channel and another portion of the payload to the receiving device on the address channel; wherein, when sending multiple sequential portions of the payload on the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the address channel by sending a first sequential portion of the multiple sequential portions on the write channel and sending a subsequent sequential portion of the multiple sequential portions on the address channel.
2. The processing system of claim 1 , wherein the portion is a second portion of the payload, wherein the other portion is a third portion of the payload, and wherein the payload further comprises a first portion, wherein, prior to sending the second and third portions of the payload, the sending device is further configured to concurrently send the first portion of the payload to the receiving device on the write channel and the address to the receiving device on the address channel, wherein the address includes a first address corresponding to the first portion, and wherein the first portion, the second portion, and the third portion of the payload are sequential portions of the payload sent to the receiving device.
3. The processing system of claim 1 , wherein the portion is a second portion of the payload, wherein the other portion is a third portion of the payload, and wherein the payload further comprises a first portion, wherein the sending device is further configured to concurrently send a fourth portion of the payload on the write channel to a first address of the receiving device and a second address to the receiving device on the address channel, wherein the first, second, third, and fourth portions of the payload are sequential portions of the payload sent to the receiving device.
4. The processing system of claim 1 , wherein the sending device comprises a first processing device and the receiving device comprises a bus interconnect, the processing system further comprising a second processing device, the bus interconnect being configured to connect the first and second processing devices to a shared resource, and wherein the first processing device is further configured to send multiple portions of the payload to the bus interconnect in response to a snoop address from the second processing device.
5. The processing system of claim 1 , wherein the bus further comprises a second address channel, the sending device being further configured to send the address to the receiving device on the address channel for write operations and to send a read address to the receiving device on the second address channel for read operations, and wherein the sending device is further configured to send an additional portion of the payload to the receiving device on the second address channel.
6. The processing system of claim 5 , wherein the sending device is further configured to concurrently send a second address to the receiving device on the address channel, a third portion of the payload to the receiving device on the write channel, and a fourth portion of the payload to the receiving device on the second address channel, wherein the third and fourth portions of the payload are sequential portions of the payload sent to the receiving device, wherein sequential data ordering preference is given to the payload data of the write channel over payload data of the second address channel.
7. The processing system of claim 1 , wherein the sending device is further configured to provide a control signal to the receiving device indicating whether the address channel is currently being used to send the address to the receiving device or send a portion of a write payload to the receiving device.
8. The processing system of claim 1 , wherein the sending device is further configured to provide a control signal on each of the address channel and the write channel, each of the control signals identifying a respective portion of the payload being sent on its corresponding channel.
9. A processing system, comprising: a receiving device; a bus having an address channel, a write channel, and a read channel; means for sending an address to the receiving device on the address channel; means for reading data from the receiving device on the read channel; and means for concurrently sending a portion of a payload from the sending device to the receiving device on the write channel and another portion of the payload from the sending device to the receiving device on the address channel, wherein, when sending multiple sequential portions of the payload on the bus concurrently, the means for sending gives data ordering preference to the write channel over the address channel by sending a first sequential portion of the multiple sequential portions on the write channel and sending a subsequent sequential portion of the multiple sequential portions on the address channel.
10. A method of communicating between a sending device and a receiving device over a bus, the bus comprising an address channel, a write channel, and a read channel, the method comprising: sending an address to the receiving device on the address channel; reading data from the receiving device on the read channel; and concurrently sending a portion of a payload from the sending device to the receiving device on the write channel and another portion of the payload from the sending device to the receiving device on the address channel, wherein, when sending multiple sequential portions of the payload on the bus concurrently, data ordering preference is given to the write channel over the address channel by sending a first sequential portion of the multiple sequential portions on the write channel and sending a subsequent sequential portion of the multiple sequential portions on the address channel.
11. The method of claim 10 , wherein the portion is a second portion of the payload, wherein the other portion is a third portion of the payload, and wherein the payload further comprises a first portion, the method further comprising: prior to sending the second and third portions of the payload, concurrently sending the first portion of the payload to the receiving device on the write channel and the address to the receiving device on the address channel, wherein the address includes a first address corresponding to the first portion, and wherein the first portion, the second portion, and the third portion of the payload are sequential portions of the payload sent to the receiving device.
12. The method of claim 10 , wherein the portion is a second portion of the payload, wherein the other portion is a third portion of the payload, and wherein the payload further comprises a first portion, the method further comprising: concurrently sending a fourth portion of the payload on the write channel to a first address of the receiving device and a second address to the receiving device on the address channel after sending the first, second, and third portions of the payload, wherein the first, second, third, and fourth portions of the payload are sequential portions of the payload sent to the receiving device.
13. The method of claim 10 , wherein the sending device comprises a first processing device and the receiving device comprises a bus interconnect, the processing system further comprising a second processing device, the bus interconnect being configured to connect the first and second processing devices to a shared resource, and wherein multiple portions of the payload are sent to the bus interconnect in response to a snoop address from the second processing device.
14. The method of claim 10 , wherein the bus further comprises a second address channel, the addressing of the receiving device on the address channel being for write operations, the method further comprising addressing the receiving device on the second address channel for read operations, and sending an additional portion of the payload to the receiving device on the second address channel.
15. The method of claim 14 , further comprising: concurrently sending a second address to the receiving device on the address channel, a third portion of the payload to the receiving device on the write channel, and a fourth portion of the payload to the receiving device on the second address channel, wherein the third and fourth portions of the payload are sequential portions of the payload sent to the receiving device, wherein sequential data ordering preference is given to payload data of the write channel over payload data of the second address channel.
16. The method of claim 10 , further comprising: providing a control signal to the receiving device indicating whether the address channel is currently being used to address the receiving device or to send a portion of a write payload to the receiving device.
17. The method of claim 14 , further comprising: providing a control signal on each of the address channel, the write channel, and the second address, each of the control signals identifying a respective portion of the payload being sent on its corresponding channel.
18. A slave device, comprising: a memory; and a bus interface configured to interface the memory to a bus having an address channel, a write channel, and a read channel, the bus interface being configured to receive an address from a bus mastering device on the address channel and to send read data to the bus mastering device on the read channel, the bus interface being further configured to concurrently receive a portion of a payload from the bus mastering device on the write channel and another portion of the payload from the bus mastering device on the address channel; wherein, when multiple sequential portions of the payload are received on the bus concurrently, a first sequential portion of the multiple sequential portions is received on the write channel and a subsequent sequential portion of the multiple sequential portions is received on the address channel according to a data ordering preference given to the write channel over the address channel.
19. The slave device of claim 18 , wherein the portion is a second portion of the payload, wherein the other portion is a third portion of the payload, and wherein the payload further comprises a first portion, wherein, prior to receiving the second and third portions, the bus interface is further configured to concurrently receive the first portion of the payload on the write channel and the address on the address channel, wherein the first portion, the second portion, and the third portion of the payload are sequential portions of the payload.
20. The slave device of claim 18 , wherein the bus interface further comprises a second address channel, the bus interface being further configured to receive the address on the address channel for write operations and to receive a read address on the second address channel for read operations, and wherein the bus interface is further configured to receive an additional portion of the payload from the bus mastering device on the second address channel.
21. The slave device of claim 20 , wherein the bus interface is further configured to concurrently receive a second address from the bus mastering device on the address channel, a third portion of the payload from the bus mastering device on the write channel, and a fourth portion of the payload from the bus mastering device on the second address channel, wherein the third and fourth portions of the payload are sequential portions of the payload sent to the bus interface of the slave, wherein sequential data ordering preference is given to payload data received from the write channel over payload data on the second address channel.
22. The slave device of claim 18 , wherein the bus interface is further configured to receive a control signal from the bus mastering device indicating whether the address channel is currently being used to send an address or a portion of a write payload.
23. The slave device of claim 20 , wherein the bus interface is further configured to receive a control signal on each of the address channel, the write channel, and the read channel, each of the control signals identifying a respective portion of the payload being sent on its corresponding channel.
24. The processing system of claim 1 , wherein the sending device is configured to implicitly address the receiving device, wherein a next sequential portion of the payload is written during an earliest available clock cycle.
25. The processing system of claim 24 , wherein each payload is transmitted in its entirety before a next payload is transmitted.
26. The method of claim 10 , wherein the sending device is configured to implicitly address the receiving device, wherein a next sequential portion of the payload is written during an earliest available clock cycle.
27. The method of claim 26 , wherein each payload is transmitted in its entirety before a next payload is transmitted.
28. The slave device of claim 18 , wherein the bus mastering device is configured to implicitly address the memory, wherein a next sequential portion of the payload is received from the bus mastering device during an earliest available clock cycle.
29. The slave device of claim 28 , wherein each payload is received in its entirety before a next payload is transmitted.
30. The processing system of claim 1 , wherein the sending device is configured to interleave portions of multiple payloads and to generate control signals including payload sequence numbers to identify each of the multiple payloads.
31. The method of claim 10 , wherein the sending device is configured to interleave portions of multiple payloads and to generate control signals including payload sequence numbers to identify each of the multiple payloads.
32. The slave device of claim 18 , wherein the bus interface is configured to interleave portions of multiple payloads and to generate control signals including payload sequence numbers to identify each of the multiple payloads.
33. A processing system comprising: a receiving device; a bus having a write address channel, a write channel, and a read address channel; and a sending device configured to send an address to the receiving device on the write address channel and to concurrently send a portion of a payload to the receiving device on the write channel and another portion of the payload to the receiving device on the read address channel, wherein, when sending multiple sequential portions of the payload on the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions on the write channel and sending a subsequent sequential portion of the multiple sequential portions on the read address channel.
34. The processing system of claim 33 , wherein the portion is a first portion of the payload, wherein the other portion is a second portion of the payload, and wherein the payload further comprises a third portion and a fourth portion, wherein the sending device is further configured to concurrently send the third portion of the payload on the write channel, the fourth portion of the payload on the read address channel, and a second address to the receiving device on the write address channel, the second address corresponding to a second payload, wherein the first, second, third, and fourth portions of the payload are sequential portions of the payload sent to the receiving device.
35. The processing system of claim 34 , wherein the second payload comprises a first portion of the second payload, a second portion of the second payload, and a third portion of the second payload, wherein, after sending the first, second, third, and fourth portions of the payload, the sending device is further configured to concurrently send the first portion of the second payload on the write channel, the second portion of the second payload on the read address channel, and the third portion of the second payload on the write address channel, wherein the first, second, and third portions of the second payload are sequential portions of the second payload sent to the receiving device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 31, 2006
January 31, 2012
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