The present invention is a noise tolerant communication protocol device and method where a clock signal input triggers an internal delay clock in an integrated circuit. Data is presented to an input pin and sampled prior to the next external clock pulse based on the internal delay clock. A data pulse value is distinguished by input signal voltage level and not by pulse length. Sampling of data bits is deferred until a signal level is most likely stable, thereby avoiding sampling during periods around edges of changing data values. Therefore, error detection and correction circuitry is not required. A time reference pulse, produced by a bus master, is measured by the protocol device to determine a data transmission rate by the master. The timing of sampling of input signaling from the master is determined by the protocol device from measurement of the time reference pulse magnitude.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic device comprising: a data input terminal, said data input terminal configured to accept an external clock pulse and a plurality of data bits from a single wire, said external clock pulse and said plurality of data bits forming a cycle; a first pulse generation means coupled to said data input terminal for producing a pulse in response to said external clock pulse; a delay means coupled to said first pulse generation means for producing a delayed pulse based on said produced pulse, said first pulse generation means and said delay means forming a portion of an internal clock; a first latching means for enabling said first pulse generation means during a period of time when said external clock pulse is present on said single wire; a second latching means enabled by said internal clock for latching each of said data bits and producing an output; and a counting means for transmitting a pulse when all data within said cycle has been latched.
2. The electronic device of claim 1 further comprising a second pulse generation means for producing an enable pulse for said second latching means from said internal clock.
3. An electronic device comprising: a data input terminal, said data input terminal configured to accept an external clock pulse and a plurality of data bits from a single wire, said external clock pulse and said plurality of data bits forming a cycle; a first pulse generator coupled to said data input terminal for producing a pulse in response to said external clock pulse; a first delay element coupled to said first pulse generator for producing a delayed pulse based on said produced pulse, said first pulse generator and said first delay element forming a portion of an internal clock; a first latch to enable said first pulse generator during a period of time when said external clock pulse is present on said single wire; a second latch enabled by said internal clock for latching each of said data bits and producing an output; and a counter for transmitting a pulse when all data bits within said cycle have been latched.
4. The electronic device of claim 3 further comprising an OR gate, a first input of said OR gate coupled to an output of said first delay element, an output of said OR gate producing a trigger for a second pulse generator.
5. The electronic device of claim 4 further comprising a second delay element coupled to an output of said second pulse generator, an output of said second delay element coupled to both said enable of said second latch and a second input of said OR gate.
6. The electronic device of claim 3 wherein said second latch is configured to latch each of said data bits during a stable period of each of said data bits.
7. A method for producing a serial data output from an external clock pulse and a plurality of data bits in series with said external clack pulse, said external clock pulse and said plurality of data bits in series forming a cycle, said method comprising: inputting said external clock pulse; producing a first pulse in response to said external clock pulse; delaying said first pulse for a first delay time; producing a secondary pulse in response to said delayed first pulse; delaying said secondary pulse for a second delay time; retrieving a first of said plurality of data bits from a first of a plurality of storage elements; providing said first of said plurality of data bits to an output latching device; activating said output latching device with said delayed secondary pulse; in response to said activating said output latching device with said delayed secondary pulse, latching data from said first of said plurality of data bits into said output latching device, the output of said output latching device producing the serial data output; and incrementing a counter with said delayed secondary pulse.
8. The method of claim 7 , wherein an output cycle is formed comprising: producing a subsequent secondary pulse; delaying said subsequent secondary pulse by said second delay time; retrieving a subsequent one of said plurality of data bits from a subsequent one of said plurality of storage elements; providing said subsequent one of said plurality of data bits to said output latching device; activating said output latching device with said delayed subsequent secondary pulse; in response to said activating said output latching device with said delayed subsequent secondary pulse, latching subsequent data from said subsequent one of said plurality of data bits into said output latching device, wherein the output cycle includes said subsequent data output from said output latching device; and incrementing said counter with said delayed subsequent secondary pulse.
9. The method of claim 8 , wherein a number of said plurality of data bits included in said output cycle corresponds to a count level of said counter.
10. The method of claim 7 further comprising: resetting an input latching device with said secondary pulse; delaying an output of said counter after a count equals a count level of said counter; and setting the input latching device with said delayed counter output to enable input of a subsequent cycle of external clock pulse and data bits.
11. The method of claim 7 wherein said counter has a count level equal to a number of said data bits in said cycle.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 19, 2011
January 31, 2012
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