Data cache with modified bit array

1. A microprocessor, comprising: first and second functional units, each coupled to and configured to access a data cache; and the data cache, comprising: a data array, having a predetermined organization, comprising: a write port by which the first functional unit writes data to a cache line of the data array; a modified bit array, having the corresponding predetermined organization as the data array, comprising: a write port by which the first functional unit sets a modified bit in the modified bit array to indicate that the corresponding cache line in the data array written to by the first functional unit has been modified; and a read port by which the second functional unit reads the modified bit from the modified bit array to determine whether or not the cache line has been modified; and a tag array, having the corresponding predetermined organization as the data array, comprising: a read port by which the second functional unit reads a partial status of the corresponding cache line in the data array, wherein the partial status, when combined with the modified bit, determines whether the cache line has been modified; wherein the tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line.

2. The microprocessor as recited in claim 1 , wherein the tag array is configured to store an address tag of the corresponding cache line in the data array, wherein the modified bit array does not store address tags.

3. The microprocessor as recited in claim 1 , further comprising: a third functional unit, coupled to and configured to access the data cache; wherein the modified bit array further comprises: a second read port by which the third functional unit reads the modified bit from the modified bit array to determine whether or not the cache line has been modified.

4. The microprocessor as recited in claim 3 , wherein the data cache further comprises: a second tag array, having the corresponding predetermined organization as the data array, comprising: a read port by which the third functional unit reads a partial status of the corresponding cache line in the data array, wherein the partial status, when combined with the modified bit, determines whether the cache line has been modified; wherein the second tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line.

5. The microprocessor as recited in claim 3 , wherein the tag array further comprises: a second read port by which the third functional unit reads a partial status of the corresponding cache line in the data array, wherein the partial status, when combined with the modified bit, determines whether the cache line has been modified.

6. The microprocessor as recited in claim 1 , wherein the first functional unit comprises a store queue unit, configured to generate a cache write operation to write the data to the cache line of the data array and to set the modified bit in the modified bit array.

7. The microprocessor as recited in claim 1 , wherein the second functional unit is configured to read the corresponding cache line from the data array to execute a load instruction.

8. The microprocessor as recited in claim 1 , wherein the second functional unit is configured to read the corresponding cache line from the data array to execute a request to evict the corresponding cache line from the data cache.

9. The microprocessor as recited in claim 1 , wherein the second functional unit is configured to compute a full status of the corresponding cache line from the modified bit read from the modified bit array and from the partial status read from the tag array, in order to execute a snoop request directed to the corresponding cache line.

10. The microprocessor as recited in claim 1 , wherein the second functional unit is configured to compute a full status of the corresponding cache line from the modified bit read from the modified bit array and from the partial status read from the tag array, in order to execute a request to evict the corresponding cache line from the cache memory.

11. The microprocessor as recited in claim 1 , wherein the second functional unit is configured to compute a full status of the corresponding cache line from the modified bit read from the modified bit array and from the partial status read from the tag array, in order to execute a store instruction.

12. The microprocessor as recited in claim 11 , wherein the first functional unit is configured to refrain from setting the modified bit in the modified bit array of the corresponding cache line if the second functional unit determines from the computed full status that the corresponding cache line is already modified.

13. The microprocessor as recited in claim 1 , the data cache further comprising: a second tag array, having the corresponding predetermined organization as the data array, comprising: a write port by which the first functional unit writes a full status of the corresponding cache line in the data array to indicate that the corresponding cache line written to by the first functional unit has been modified.

14. The microprocessor as recited in claim 13 , the second tag array also having a read port by which the first functional unit reads the full status of the corresponding cache line in the data array.

15. The microprocessor as recited in claim 1 , wherein when the data cache allocates the corresponding cache line into the data cache, the first functional unit is configured to reset the modified bit in the modified bit array to indicate that the corresponding cache line in the data array is unmodified.

16. The microprocessor as recited in claim 1 , wherein the tag array further comprises: a write port by which the second functional unit writes the partial status of the corresponding cache line in the data array; wherein when the second functional unit writes the partial status of the corresponding cache line to invalidate the corresponding cache line, the first functional unit is configured to reset the corresponding modified bit in the modified bit array.

17. A method for first and second functional units to access a data cache in a microprocessor, the data cache having a data array with a predetermined organization and a tag array having the corresponding predetermined organization, the method comprising: writing data to a cache line of the data array via a write port of the data array, wherein said writing data is performed by the first functional unit; setting a modified bit in a modified bit array of the data cache to indicate that the corresponding cache line in the data array written to by the first functional unit has been modified, wherein the modified bit array has the corresponding predetermined organization as the data array, wherein said setting a modified bit is performed by the first functional unit via a write port of the modified bit array; reading the modified bit from the modified bit array to determine whether or not the cache line has been modified, wherein said reading the modified bit is performed by the second functional unit via a read port of the modified bit array; and reading a partial status of the corresponding cache line in the data array, wherein the partial status, when combined with the modified bit, indicates whether the cache line has been modified, wherein said reading a partial status is performed by the second functional unit via a read port of the tag array, wherein the tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line.

18. The method as recited in claim 17 , wherein the tag array is configured to store an address tag of the corresponding cache line in the data array, wherein the modified bit array does not store address tags.

19. The method as recited in claim 17 , wherein the microprocessor further includes a third functional unit for accessing the data cache, the method further comprising: reading the modified bit from the modified bit array a second time to determine whether or not the cache line has been modified, wherein said reading the modified bit a second time is performed by the third functional unit via a second read port of the modified bit array.

20. The method as recited in claim 19 , wherein the data cache further includes a second tag array, having the corresponding predetermined organization as the data array, the method further comprising: reading a partial status of the corresponding cache line in the data array a second time, wherein the partial status, when combined with the modified bit, indicates whether the cache line has been modified, wherein said reading a partial status of the cache line a second time is performed the third functional unit via a read port of the second tag array, wherein the second tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line.

21. The method as recited in claim 19 , the method further comprising: reading a partial status of the corresponding cache line in the data array a second time, wherein the partial status, when combined with the modified bit, indicates whether the cache line has been modified, wherein said reading a partial status a second time is performed by the third functional unit via a second read port of the tag array.

22. The method as recited in claim 17 , wherein the first functional unit comprises a store queue unit, configured to generate a cache write operation to perform said writing data to a cache line of the data array and said setting a modified bit in a modified bit array.

23. The method as recited in claim 17 , further comprising: reading the corresponding cache line from the data array to execute a load instruction, wherein said reading the corresponding cache line is performed by the second functional unit.

24. The method as recited in claim 17 , further comprising: reading the corresponding cache line from the data array to execute a request to evict the corresponding cache line from the data cache, wherein said reading the corresponding cache line is performed by the second functional unit.

25. The method as recited in claim 17 , further comprising: computing a full status of the corresponding cache line from the modified bit read from the modified bit array and from the partial status read from the tag array, in order to execute a snoop request directed to the corresponding cache line, wherein said computing a full status of the corresponding cache line is performed by the second functional unit.

26. The method as recited in claim 17 , further comprising: computing a full status of the corresponding cache line from the modified bit read from the modified bit array and from the partial status read from the tag array, in order to execute a request to evict the corresponding cache line from the cache memory, wherein said computing a full status of the corresponding cache line is performed by the second functional unit.

27. The method as recited in claim 17 , further comprising: computing a full status of the corresponding cache line from the modified bit read from the modified bit array and from the partial status read from the tag array, in order to execute a store instruction, wherein said computing a full status of the corresponding cache line is performed by the second functional unit.

28. The method as recited in claim 27 , further comprising: refraining from setting the modified bit in the modified bit array of the corresponding cache line if the second functional unit determines from the computed full status that the corresponding cache line is already modified.

29. The method as recited in claim 17 , wherein the data cache further includes a second tag array, having the corresponding predetermined organization as the data array, the method further comprising: writing a full status of the corresponding cache line in the data array to indicate that the corresponding cache line written to by the first functional unit has been modified, wherein said writing a full status of the corresponding cache line is performed by the first functional unit via a write port of the second tag array.

30. The method as recited in claim 29 , further comprising: reading the full status of the corresponding cache line in the data array, wherein said reading the full status of the corresponding cache line is performed by the first functional unit via a read port of the second tag array.

31. The method as recited in claim 17 , further comprising: allocating the corresponding cache line into the data cache; and resetting the modified bit in the modified bit array to indicate that the corresponding cache line in the data array is unmodified, in response to said allocating the corresponding cache line, wherein said resetting the modified bit is performed by the first functional unit.

32. The method as recited in claim 17 , further comprising: writing the partial status of the corresponding cache line in the data array to invalidate the corresponding cache line, wherein said writing the partial status of the corresponding cache line to invalidate the corresponding cache line is performed by the second functional unit via a write port of the tag array; and resetting the corresponding modified bit in the modified bit array, wherein said resetting the corresponding modified bit is performed by the first functional unit.

33. A computer program product for use with a computing device, the computer program product comprising: a computer usable storage medium, having computer readable program code embodied in said medium, for specifying microprocessor, the computer readable program code comprising: first program code for specifying first and second functional units, each coupled to and configured to access a data cache; and second program code for specifying the data cache, the data cache comprising: a data array, having a predetermined organization, comprising: a write port by which the first functional unit writes data to a cache line of the data array; a modified bit array, having the corresponding predetermined organization as the data array, comprising: a write port by which the first functional unit sets a modified bit in the modified bit array to indicate that the corresponding cache line in the data array written to by the first functional unit has been modified; and a read port by which the second functional unit reads the modified bit from the modified bit array to determine whether or not the cache line has been modified; and a tag array, having the corresponding predetermined organization as the data array, comprising: a read port by which the second functional unit reads a partial status of the corresponding cache line in the data array, wherein the partial status, when combined with the modified bit, indicates whether the cache line has been modified; wherein the tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line.