A system, that includes: a memory unit adapted to store state duration statistics indicative of possible low power state durations and probabilities associates with the possible state durations; and a power controller, adapted to: receive a request to cause a circuit to enter a next state, and assist in causing the circuit to enter the next state if during a delay period that follows a reception of the request the power controller does not receive a request to cause the circuit to exit the next state; wherein the delay period is determined in response to: (i) the next state duration statistics, (ii) power saving gained from entering the next state; and (iii) power penalty associated with entering the next state and exiting the next state.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A system, comprising: a memory unit adapted to store state duration statistics of at least one state; and a power controller, adapted to: receive a request to cause a circuit to change its state from a current state to a next state; wherein the current state is associated with a different power consumption than the next state; and assist in causing the circuit to enter the next state if during a next state delay period that follows a reception of the request the power controller does not receive a request to cause the circuit to exit the next state; wherein the next state delay period is determined in response to: state duration statistics of the next state; power saving gained from entering the next state; and power penalty associated with entering the next state and exiting the next state.
2. The system according to claim 1 comprising a statistics module that is adapted to calculate the next state duration statistics.
3. The system according to claim 1 comprising a delay period module that is adapted to determine the next state delay period.
4. The system according to claim 3 wherein the delay period module is adapted to determine the next state delay period by: integrating the probabilities associated the possible next state durations to provide a first integral; multiplying each point in the integral by a power saving gained from entering the next state to provide a second integral; finding a crossing point of the second integral and a line that represents that the power penalty associated with entering the next state; and determining the next state delay period in response to the crossing point.
5. The system according to claim 1 wherein the power controller is adapted to assist in causing the circuit to exit the next state in response to the next state duration statistics.
6. The system according to claim 1 wherein the next state is a low power state.
7. The system according to claim 1 wherein the next state is an intermediate power state.
8. A method for power management, the method comprising: receiving a request to cause a circuit to change its state from a current state to a next state, wherein the current state is associated with a different power consumption than the next state; and assisting in causing the circuit to enter the next state if not receiving, during a next state delay period that follows the receiving of the request, a request to cause the circuit to exit the next state; wherein the next state delay period is determined in response to: next state duration statistics; power saving gained from entering the next state; and power penalty associated with entering the next state and exiting the next state.
9. The method according to claim 8 comprising calculating the next state duration statistics.
10. The method according to claim 8 comprising determining the delay period.
11. The method according to claim 8 comprising determining the delay period by: integrating the probabilities associated the possible next state durations to provide a first integral; multiplying each point in the integral by a power saving gained from entering the next state to provide a second integral; finding a crossing point of the second integral and a line that represents that the power penalty associated with entering the next state; and determining the delay period in response to the crossing point.
12. The method according to claim 8 comprising assisting in causing the circuit to exit the next state in response to the next state duration statistics.
13. The method according to claim 8 wherein the next state is a low power state.
14. The method according to claim 8 wherein the next state is an intermediate power state.
15. A computer program product that comprises a non-transitory computer program medium that stores instructions for: receiving a request to cause a circuit to enter a next state; and assisting in causing the circuit to enter the next state if not receiving, during a delay period that follows the receiving of the request, a request to cause the circuit to exit the next state; wherein the delay period is determined in response to: next state duration statistics; power saving gained from entering the next state; and power penalty associated with entering the next state and exiting the next state.
16. The computer program product according to claim 15 comprising instructions for calculating the next state duration statistics.
17. The computer program product according to claim 15 comprising instructions for determining the delay period.
18. The computer program product according to claim 17 comprising instructions for determining the delay period by: integrating the probabilities associated the possible next state durations to provide a first integral; multiplying each point in the integral by a power saving gained from entering the next state to provide a second integral; finding a crossing point of the second integral and a line that represents that the power penalty associated with entering the next state; and determining the delay period in response to the crossing point.
19. The method according to claim 15 comprising instructions for assisting in causing the circuit to exit the next state in response to the next state duration statistics.
20. The computer program product according to claim 15 wherein the next state is a low power state.
21. The computer program product according to claim 15 wherein the next state is an intermediate power state.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 25, 2008
February 7, 2012
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