An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2), the ECC controller comprising: a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method; and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.
2. The controller of claim 1 , wherein the second ECC block decodes data read from the flash memory using the second error correcting method and the first ECC block decodes data read from the flash memory using the first error correcting method.
3. The controller of claim 1 , wherein the first error correcting method is a linear block method and the second error correcting method is an ML (maximum likelihood) method.
4. The controller of claim 1 , wherein the second ECC block generates the second ECC data by adding parity data to the program data and the first ECC data.
5. The controller of claim 1 , wherein the flash memory device is one of a NAND flash memory device, a NOR flash memory device, a PRAM (phase-change random access memory) device, and an MRAM device (magnetoresistive random access memory).
6. A memory system comprising: a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2); and a memory controller which controls the flash memory device, wherein the memory controller comprises an ECC controller which encodes data to be stored in the flash memory device using a first error correcting method and a second error correcting method, wherein the first error correcting method is a linear block method and the second error correcting method is an ML (maximum likelihood) method, and wherein the ECC controller comprises: a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to the linear block method; and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to the maximum likelihood method, the program data, the first ECC data, and the second ECC data being stored simultaneously in the flash memory device.
7. The system of claim 6 , wherein the second ECC block corrects an error of data read from the flash memory device by using the second ECC data included in the data read from the flash memory device, and the first ECC block corrects an error of the read data using the first ECC data included in read data output from the second ECC block.
8. The system of claim 6 , wherein the second ECC block generates the second ECC data by adding parity data to the program data and the first ECC data.
9. The system of claim 6 , wherein the flash memory device comprises a first storage region which stores the program data, and a second storage region which stores the first ECC data and the second ECC data.
10. The system of claim 9 , wherein respective memory cells of the first storage region store an M-bit data, and respective memory cells of the second storage region store a 1-bit data.
11. The system of claim 6 , wherein the memory controller is mounted on a main board of a computing system.
12. The system of claim 6 , wherein the flash memory device and the memory controller constitute a memory card.
13. A memory system comprising: a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2); and a memory controller which controls the flash memory device, wherein the memory controller comprises: a first ECC block which generates a CRC (cyclic redundancy check) value from a program data to be stored in the flash memory device and outputs a first data pattern; and a second ECC block which generates a first ECC data from the first data pattern and outputs a second data pattern according to a first error correcting method; and a third ECC block which generates a second ECC data from the second data pattern and outputs a third data pattern according to a second error correcting method.
14. The system of claim 13 , wherein the first error correcting method is a linear block method and the second error correcting method is an ML (maximum likelihood) method.
15. The system of claim 13 , wherein the third ECC block corrects an error of data read from the flash memory device using the second ECC data included in the data read from the flash memory device, the second ECC block corrects an error of the read data using the first ECC data included in read data output from the third ECC block, and the first ECC block detects whether the read data has an error using the CRC value included in read data output from the second ECC block.
16. The system of claim 15 , wherein the third ECC block generates the second ECC data by adding parity data to the second data pattern.
17. The system of claim 15 , wherein the flash memory device comprises a first storage region which stores the program data, and a second storage region which stores the CRC value, the first ECC data, and the second ECC data.
18. The system of claim 17 , wherein respective memory cells of the first storage region store an M-bit data, and respective memory cells of the second storage region store a 1-bit data.
19. A method for correcting an error of an M-bit data (M being a positive integer equal to or greater than 2) stored in a flash memory device, the method comprising: generating a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method; and generating a second ECC data from the first ECC data and the program data output from a first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being simultaneously stored in the flash memory device.
20. The method of claim 19 , further comprising: correcting an error of data read from the flash memory device using the second ECC data included in the data read from the flash memory device; and correcting an error of the read data using the first ECC data included in read data output from a second ECC block.
21. The method of claim 19 , wherein the first error correcting method is a linear block method, and the second error correcting method is an ML (maximum likelihood) method.
22. The method of claim 19 , wherein the second ECC data is generated by adding parity data to the program data and the first ECC data.
23. The method of claim 19 , wherein the flash memory device is one of a NAND flash memory device, a NOR flash memory device, a PRAM, and an MRAM.
24. The method of claim 19 , further including: storing the program data in a first storage region of the flash memory device and storing the first ECC data and the second ECC data in a second storage region of the flash memory device.
25. The method of claim 24 , further including storing M-bit data in respective memory cells of the first storage region and storing 1-bit data in respective memory cells of the second storage region.
26. A method for correcting an error of an M-bit data (M being a positive integer equal to or greater than 2) stored in a flash memory device, the method comprising: generating a CRC (cyclic redundancy check) value from a program data to be stored in the flash memory device and outputting a first data pattern; generating a first ECC data from the first data pattern and outputting a second data pattern according to a first error correcting method; and generating a second ECC data from the second data pattern and outputting a third data pattern according to a second error correcting method, the third data pattern including the program data, the CRC value, the first ECC data, and the second ECC data being stored in the flash memory device.
27. The method of claim 26 , further comprising: correcting an error in data read from the flash memory device using the second ECC data included in the data read from the flash memory device; correcting an error of the read data using the first ECC data included in the read data output from a third ECC block; and detecting whether the read data has an error using the CRC value included in the read data output from a second ECC block.
28. The method of claim 26 , wherein the second ECC data is generated by adding parity data to the second data pattern.
29. The method of claim 26 , further including storing the program data in a first storage region of the flash memory device and storing the CRC value, the first ECC data, and the second ECC data in a second storage region of the flash memory device.
30. The method of claim 29 , further including storing M-bit data in respective memory cells of the first storage region and storing 1-bit data in respective memory cells of the second storage region.
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April 19, 2007
February 7, 2012
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