Patentable/Patents/US-8114787
US-8114787

Integrated circuit nanowires

PublishedFebruary 14, 2012
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Implementations of encapsulated nanowires are disclosed.

Patent Claims
9 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for producing encapsulated nanowires, comprising: providing a substrate having a surface layer; patterning the surface layer to form nanometer-sized features; disposing a conductive material in the nanometer-sized features using a metal precursor conveyed in a supercritical carbon dioxide to form nanowires on the substrate; removing the surface layer; and forming one or more insulating monolayers to entirely encapsulate the nanowires, wherein forming each of the one or more insulating monolayers includes disposing a self-assembled monolayer (SAM) including octadecylsiloxane (ODS) at a temperature of less than about 350° C. and oxidizing the ODS by an exposure of ultraviolet radiation.

2

2. The method of claim 1 , wherein the surface layer comprises a photoresist layer and wherein patterning the surface layer comprises performing lithography to pattern the photoresist layer.

3

3. The method of claim 2 , wherein performing lithography comprises performing one of nanoimprint lithography, electron beam lithography or extreme ultraviolet photolithography.

4

4. The method of claim 1 , wherein the insulating material comprises silicon dioxide.

5

5. The method of claim 1 , wherein the conductive material comprises copper, aluminum, tungsten, or any combination thereof.

6

6. The method of claim 1 , wherein the surface layer comprises a stressed silicon dioxide layer and wherein patterning the surface layer comprises forming nanometer-sized cracks in the stressed silicon dioxide layer.

7

7. The method of claim 6 , further comprising: patterning the substrate prior to disposing the surface layer on the substrate.

8

8. The method of claim 6 , wherein disposing the conductive material in the nanometer-sized features comprises disposing the metal in the nanometer-sized cracks.

9

9. The method of claim 1 , wherein disposing the conductive material in the nanometer-sized features comprises disposing the conductive material in the nanometer-sized features at temperatures of less than about 350° C.

Classification Codes (CPC)

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Patent Metadata

Filing Date

February 19, 2009

Publication Date

February 14, 2012

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