A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting a component over the first substrate; mounting a stack substrate over the component, the stack substrate having an inner pad and an outer pad connected to the first substrate; mounting a first exposed interconnect on the outer pad; forming a first encapsulation over the stack substrate, the first exposed interconnect partially exposed and the inner pad partially exposed in a recess of the first encapsulation; and mounting a second exposed interconnect on the inner pad.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacture of an integrated circuit packaging system comprising: providing a first substrate; mounting a component over the first substrate; mounting a stack substrate over the component, the stack substrate having an inner pad and an outer pad connected to the first substrate; mounting a first exposed interconnect on the outer pad; forming a first encapsulation over the stack substrate, the first exposed interconnect partially exposed and the inner pad partially exposed in a recess of the first encapsulation; and mounting a second exposed interconnect on the inner pad.
2. The method as claimed in claim 1 further comprising: providing a second substrate; connecting a first device to the second substrate; and attaching the second substrate to the first exposed interconnect.
3. The method as claimed in claim 1 further comprising connecting a second device to the stack substrate.
4. The method as claimed in claim 1 further comprising: forming a second encapsulation with the second exposed interconnect partially exposed; and forming an inter-package underfill between the second encapsulation and the stack substrate.
5. The method as claimed in claim 1 further comprising: providing a second substrate having a second substrate bottom surface and a second substrate top surface opposite the second substrate bottom surface; attaching a first device to the second substrate top surface; attaching a third device to the second substrate bottom surface; and attaching the second substrate to the first exposed interconnect.
6. A method of manufacture of an integrated circuit packaging system comprising: providing a first substrate; mounting a component over the first substrate; mounting a stack substrate over the component, the stack substrate having an inner pad and an outer pad adjacent the inner pad and along the periphery of the stack substrate; connecting a stack substrate interconnect to the first substrate and the outer pad; mounting a first exposed interconnect on the outer pad; forming a first encapsulation over the stack substrate, the first exposed interconnect partially exposed and the inner pad partially exposed in a recess of the first encapsulation; and mounting a second exposed interconnect on the inner pad.
7. The method as claimed in claim 6 further comprising: forming the first exposed interconnect having a first wide body and a first narrow top over the first wide body; and attaching a second substrate, having a second substrate top surface and a second substrate terminal extended above the second substrate top surface, to the first exposed interconnect with the second substrate terminal connected to the first narrow top.
8. The method as claimed in claim 6 further comprising: forming the first exposed interconnect having a first wide body and a first narrow top over the first wide body; and attaching a second substrate to the first exposed interconnect with the second substrate having a second substrate terminal connected to the first narrow top extended above the first encapsulation.
9. The method as claimed in claim 6 further comprising: forming a second substrate having a second substrate bottom surface and a second substrate top surface attached to the first exposed interconnect; and attaching an external connector to the second substrate bottom surface.
10. The method as claimed in claim 6 further comprising connecting a flip-chip to the stack substrate.
11. An integrated circuit packaging system comprising: a first substrate; a component over the first substrate; a stack substrate over the component, the stack substrate having an inner pad and an outer pad connected to the first substrate; a first exposed interconnect on the outer pad; a first encapsulation over the stack substrate, the first exposed interconnect partially exposed and the inner pad partially exposed in a recess of the first encapsulation; and a second exposed interconnect on the inner pad.
12. The system as claimed in claim 11 further comprising: a second substrate attached to the first exposed interconnect; and a first device connected to the second substrate.
13. The system as claimed in claim 11 further comprising a second device connected to the stack substrate.
14. The system as claimed in claim 11 further comprising: a second encapsulation with the second exposed interconnect partially exposed; and an inter-package underfill between the second encapsulation and the stack substrate.
15. The system as claimed in claim 11 further comprising: a second substrate attached to the first exposed interconnect with the second substrate having a second substrate bottom surface and a second substrate top surface opposite the second substrate bottom surface; a first device attached to the second substrate top surface; and a third device attached to the second substrate bottom surface.
16. The system as claimed in claim 11 further comprising a stack substrate interconnect connected to the first substrate and the outer pad with the outer pad adjacent the inner pad and along the periphery of the stack substrate.
17. The system as claimed in claim 16 wherein: the first exposed interconnect includes a first wide body and a first narrow top over the first wide body; and further comprising: a second substrate, having a second substrate top surface and a second substrate terminal extended above the second substrate top surface, attached to the first exposed interconnect with the second substrate terminal connected to the first narrow top.
18. The system as claimed in claim 16 wherein: the first exposed interconnect includes a first wide body and a first narrow top over the first wide body; and further comprising: a second substrate attached to the first exposed interconnect with the second substrate having a second substrate terminal connected to the first narrow top extended above the first encapsulation.
19. The system as claimed in claim 16 further comprising: a second substrate having a second substrate bottom surface and a second substrate top surface attached to the first exposed interconnect; and an external connector attached to the second substrate bottom surface.
20. The system as claimed in claim 16 further comprising a flip-chip connected to the stack substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 8, 2009
February 14, 2012
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