The present invention is a method, circuit and system for erasing a non-volatile memory cell. A shunting element (e.g. transistor) may be introduced and/or activated between bit-lines to which one or more NVM cells being erased are connected. The shunting element may be located and/or activated across two bit-lines defining a given column of cells, where one or a subset of cells from the column may be undergoing an erase operation or procedure. The shunting element may be located, and/or activated, at some distance from the two bit-lines defining the given column of cells, and the shunting element may be electrically connected to the bit-lines defining the column through select transistors and/or through global bit-lines.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of erasing a subset of non-volatile memory cells (“NVM”) within a column segment of NVM cells having a first bit-line connected a first terminal of the NVM cells and a second bit line connected to the second terminal of the NVM cells, said method comprising: shunting through a shunting element the first bit-line to the second bit-line substantially concurrently to applying an erase voltage to a gate terminal of the subset of NVM cells to be erased.
2. The method according to claim 1 , wherein shunting the first bit-line to the second bit-line includes activating a shunting element located on the same column as the sub-set of cells.
3. The method according to claim 1 , wherein shunting the first bit-line to the second bit-line includes activating a shunting element located outside the same column as the sub-set of cells.
4. The method according to claim 3 , further comprising electrically connecting the shunting element located outside the same column as the sub-set of cells with the same column as the sub-set of cells through one or more select transistors.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 6, 2005
February 14, 2012
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.