A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a reference frequency when all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal, a delay lock reset unit generating a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and a direct phase detector controlling a coarse locking window on the basis of the check signal and generating a pair of phase detection signals indicating logic levels of the external clock. According to this configuration, since the coarse locking window is controlled as per a frequency band, it is possible to prevent a failure of a coarse locking and to achieve an improved circuit performance.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A delay locked loop circuit comprising: a delay locked loop configured to receive an external clock and perform a delay lock process; a frequency detector configured to delay an input frequency signal which is obtained by delaying the external clock to generate a plurality of strobe signals, and output a check signal indicating whether the frequency of the input frequency signal is equal to or lower than a reference frequency if all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal; and a direct phase detector configured to receive the check signal from the frequency detector, control a coarse locking window of the delay locked loop circuit on the basis of the check signal, and generate a pair of phase detection signals indicating logic levels of the external clock.
2. The delay locked loop circuit of claim 1 , further comprising: a delay lock reset unit configured to generate a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform the delay lock process, and output the reset signal and the activation signal to the frequency detector and the delay locked loop, respectively.
3. The circuit of claim 2 , wherein the delay lock reset unit includes a counter configured to set a frequency detection time period which is the maximum time period required for the frequency detector to detect the frequency of the input frequency signal.
4. The circuit of claim 1 , wherein a number of the plurality of strobe signals is 3.
5. The circuit of claim 4 , wherein a time interval between first and second strobe signals of the three strobe signals indicates the reference frequency and a time interval between the second strobe signal and a third strobe signal of the three strobe signals indicates a marginal delay time interval based on a distortion in a duty cycle of the input frequency signal.
6. The circuit of claim 4 , wherein the direct phase detector is configured to pass the input frequency signal through a delay path to generate a later phase detection signal of the pair of phase detection signals when the check signal indicates that the frequency of the input frequency signal is equal to or lower than the reference frequency.
7. The circuit of claim 1 , wherein the first-status section of the input frequency signal is a high-level section.
8. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells; a read/write circuit connected to the plurality of memory cells; a delay locked loop circuit including a delay locked loop configured to delay an external clock to generate an internal clock, and apply the internal clock to the read/write circuit; a frequency detector configured to delay an input frequency signal which is obtained by delaying the external clock to generate a plurality of strobe signals and output a check signal indicating whether the frequency of the input frequency signal is equal to or lower than a reference frequency if all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal; a delay lock reset unit configured to generate a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and output the reset signal and the activation signal to the frequency detector and the delay locked loop, respectively; and a direct phase detector configured to receive the check signal from the frequency detector, control a coarse locking window of the delay locked loop circuit on the basis of the check signal, and generate a pair of phase detection signals indicating logic levels of the external clock.
9. The device of claim 8 , wherein a number of the plurality of strobe signals is 3.
10. The device of claim 9 , wherein the first-status section of the input frequency signal is a high-level section.
11. The device of claim 10 , wherein a time interval between first and second strobe signals of the three strobe signals indicates the reference frequency and a time interval between the second strobe signal and a third strobe signal of the three strobe signals indicates a marginal delay time interval based on a distortion in a duty cycle of the input frequency signal.
12. A delay locked loop circuit comprising: a delay locked loop configured to receive an external clock and perform a delay lock process; a frequency detector configured to generate a plurality of strobe signals by delaying an input frequency signal which is a delayed signal of the external clock, the frequency detector being configured to output a check signal indicating a frequency of the input frequency signal based on one or more of the plurality of strobe signals; and a direct phase detector configured to control a coarse locking window of the delay locked loop circuit on the basis of the check signal, and generate a pair of phase detection signals indicating logic levels of the external clock.
13. The delay lock loop circuit of claim 12 , further comprising: a delay lock reset unit configured to generate a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform the delay lock process, and output the reset signal and the activation signal to the frequency detector and the delay locked loop, respectively.
14. The circuit of claim 13 , wherein the delay lock reset unit includes a counter configured to set a frequency detection time period which is the minimum time period required for the frequency detector to detect the frequency of the input frequency signal.
15. The delay locked loop circuit of claim 12 , wherein the frequency detector is configured to output the check signal if all of the plurality of strobe signals have rising edges that occur during a high portion of one cycle of the input frequency signal, or if all of the plurality of strobe signals have rising edges that occur during a low portion of one cycle of the input frequency signal.
16. The delay locked loop circuit of claim 12 , wherein the direct phase detector is configured to receive the check signal from the frequency detector.
17. The circuit of claim 12 , wherein the check signal indicates that the frequency of the input frequency signal is equal to or lower than a reference frequency based on the one or more of the plurality of strobe signals.
18. The circuit of claim 17 , wherein a number of the plurality of strobe signals is 3.
19. The circuit of claim 18 , wherein the frequency detector includes a first delay unit configured to control a first time interval between first and second strobe signals of the three strobe signal, and a second delay unit configured to control a second time interval between the second strobe signal and a third strobe signal of the three strobe signals, the first delay unit being configured to control the first time interval to correspond to the reference frequency, and the second delay unit being configured to control the second time interval to correspond to a marginal delay time interval based on a distortion in a duty cycle of the input frequency signal.
20. The circuit of claim 18 , wherein the direct phase detector is configured to pass the input frequency signal through a delay path to generate a later phase detection signal of the pair of phase detection signals based on receiving the check signal.
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February 24, 2010
February 21, 2012
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