A circuit is operated to detect unstable memory cells from among a plurality of memory cells in at least one page. A determination is made from an initial status of data stored in a memory cell whether no read error occurs when the data is read at a standard read voltage level, whether a read error occurs and the read error is correctable, and whether a read error occurs and the read error is uncorrectable. Responsive to determining that a read error occurs that is correctable, a further determination is made as to whether the memory cell is correctable by reading the data stored in the memory cell at a correction read voltage level, which has a different voltage level from the standard read voltage level, and by determining whether a read error occurring in the data read at the correction read voltage level is correctable or uncorrectable.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of operating a circuit to detect unstable memory cells from among a plurality of memory cells in at least one page, the method comprising: determining from an initial status of data stored in a memory cell whether no read error occurs when the data is read at a standard read voltage level, whether a read error occurs and the read error is correctable, and whether a read error occurs and the read error is uncorrectable; and responsive to determining that a read error occurs that is correctable, further determining whether the memory cell is correctable by reading the data stored in the memory cell at a correction read voltage level, which has a different voltage level from the standard read voltage level, and by determining whether a read error occurring in the data read at the correction read voltage level is correctable or uncorrectable.
2. The method of claim 1 , further comprising responding to a determination that no read error occurs by determining that data stored in the memory cell or in a page of the memory cell is stable, and responding to a determination that the read error is uncorrectable by determining that data stored in the memory cell or in the page of the memory cell is not to be used for data access by a host device.
3. The method of claim 2 , wherein the determining from an initial status of data stored in a memory cell comprises: determining from the initial status of the data stored in the memory cell whether an uncorrectable read error has occurred; and responsive to determining that no uncorrectable read error has occurred, determining whether there is no read error.
4. The method of claim 1 , wherein: the determining from an initial status of data stored in a memory cell comprises first determining a number of memory cells in which a correctable read error occurs when the data stored in the memory cells are read at the standard read voltage level; and the further determining whether the memory cell is correctable comprises determining whether a read error occurring when the data stored in the memory cells are read using the correction read voltage level is correctable or uncorrectable.
5. The method of claim 4 , wherein the determining whether a read error occurring when the data stored in the memory cells are read using the correction read voltage level is correctable or uncorrectable comprises: determining whether the read error is uncorrectable; responsive to determining that read error is correctable, second determining a number of memory cells in which a correctable read error occurs when the data stored in the memory cells are read using the correction read voltage level; and determining whether the number of memory cells in which a correctable read error occurs when read at the correction read voltage level is larger than a number of memory cells in which a correctable read error occurs when read at the standard read voltage level.
6. The method of claim 5 , further comprising: responsive to a determination that the read error is uncorrectable, determining that data in a memory cell or in a page of the memory is not to be used for data access by a host and restricting access by the host thereto; responsive to determining that the number of memory cells in which a correctable read error occurs when read at the correction read voltage level is larger than a number of memory cells in which a correctable read error occurs when read at the standard read voltage level, determining that the data stored in the memory cell or in the page of the memory cell is not to be used for data access by the host and restricting access by the host thereto; and responsive to the number of memory cells in which a correctable read error occurs when read at the correction read voltage level is less than the number of memory cells in which a correctable read error occurs when read at the standard read voltage level, determining that the data stored in the memory cell or in the page of the memory cell is stable and allowed to be accessed by the host.
7. The method of claim 1 , wherein the determining from an initial status of data stored in a memory cell and the determining whether the memory cell is correctable are repeatedly performed on a plurality of pages.
8. The method of claim 1 , wherein the determining whether the memory cell is correctable comprises repetitively reading the memory cell at a plurality of different voltage levels.
9. A method of operating a circuit to detect unstable memory cells from among a plurality of memory cells in at least one page, the method comprising: determining from an initial status of data stored in a memory cell whether no read error occurs when the data is read at a standard read voltage level, whether a read error occurs and the read error is correctable, and whether a read error occurs and the read error is uncorrectable; responsive to determining that a read error occurs that is correctable, further determining whether the memory cell is correctable by reading the data stored in the memory cell at a correction read voltage, which has a different voltage level from the standard read voltage level, and by determining whether a read error occurring in the data read at the correction read voltage level is correctable or uncorrectable; and repeatedly performing the determining whether the memory cell is correctable by reading the data stored in the memory cell at a plurality of different correction read voltages.
10. A memory system comprising: a memory; and a memory controller that is configured to control the memory, wherein the memory controller reads data stored in a memory cell of the memory or data stored in a memory page of the memory cell of the memory using a standard read voltage level and reads the data stored in the memory cell of the memory or data stored in a memory page of the memory cell of the memory using a correction read voltage level that is different than the standard read voltage level, and is configured to determine data access by a host to the memory cell is to be allowed responsive to detecting whether a read error occurred in the memory cell when read at the correct read voltage level and when read at the standard read voltage level.
11. A memory system comprising: a solid state disc (SDD) comprising a plurality of memory cells; and a memory controller that is configured to write data in the SDD and to read the data from the SDD, wherein the memory controller sequentially uses a standard write voltage to read data from the memory cells and uses a correction read voltage, which is different from the standard read voltage, to read data from the memory cells, and determines a distribution of read errors in the data read from the memory cells at the standard read voltage and at the correction read voltage, and determines whether data stored in the plurality of memory cells is valid responsive to the determined distribution of read errors.
12. The memory system of claim 11 , wherein the memory controller comprises a central processing unit (CPU) and an error correction code (ECC) unit, wherein the CPU supplies the standard read voltage to the SSD and determines the distribution of errors when the data is read using the standard read voltage, and the ECC unit determines whether an error occurs in the data stored in the SSD from the determined distribution, and responsive to determining that an error occurred in the data stored in the SSD, the CPU determines whether the error is correctable or uncorrectable, and responsive to determining that the error is uncorrectable, the CPU instructs a host not to use the data stored in the memory cell, and responsive to determining that the error is correctable, the CPU supplies the correction read voltage to the SSD and determines the distribution of errors in the data read using the correction read voltage, and the ECC unit determines whether the error is correctable or uncorrectable according to the determined distribution of errors in the data read using the correction read voltage, and the CPU corrects the data stored in the SSD according to the determined distribution of errors.
13. The memory system of claim 12 , wherein the memory controller further comprises a random access memory (RAM), and when correcting the data stored in the SSD, the CPU stores the data stored in the memory cell in the RAM and then writes the data stored in the RAM again in the memory cell of the SSD.
14. The memory system of claim 11 , wherein the SSD comprises a flash memory.
15. The memory of claim 11 , wherein validity of the data stored in the SSD is determined based on data included in one of sections of the SSD.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 5, 2010
February 21, 2012
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