A method, apparatus, and system for dynamic adjustment of an error control coding (ECC) code rate are disclosed. In one embodiment, a code rate may be changed from a first code rate to a second code rate in response to a change in a bit error rate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: a memory array; an Error Control Coding (ECC) engine coupled to the memory array; and a bit error monitor coupled to the ECC engine, wherein the ECC engine is to provide a signal to the bit error monitor for an uncorrectable codeword, and wherein the bit error monitor is to trigger a code rate change for the ECC engine based on a bit error rate.
2. The apparatus of claim 1 , wherein the ECC engine is further to correct hit errors in correctable codewords, to determine a number of bits corrected in each correctable codeword, and to provide the number of bits corrected in each correctable codeword to the bit error monitor.
3. The apparatus of claim 1 , wherein the bit error rate is an outgoing error rate.
4. The apparatus of claim 1 , wherein the bit error rate is an incoming bit error rate.
5. The apparatus of claim 1 , wherein the memory array, the ECC engine, and the bit error monitor are part of a memory device.
6. The apparatus of claim 1 , wherein the memory device is a NAND flash memory device.
7. The apparatus of claim 1 , wherein the ECC engine and the bit error monitor are part of a memory controller device and wherein the memory array is part of a flash memory device.
8. A system comprising: an interconnect; a controller coupled to the interconnect; a wireless interface coupled to the interconnect; and a memory device coupled to the interconnect, wherein the memory device includes a memory array, an Error Control Coding (ECC) engine coupled to the memory array, and a bit error monitor coupled to the ECC engine, wherein the ECC engine is to provide a signal to the bit error monitor for an uncorrectable codeword, and wherein the bit error monitor is to trigger a code rate change for the ECC engine based on a bit error rate.
9. The system of claim 8 , wherein the memory device is a NAND flash memory device.
10. The system of claim 9 , wherein the memory array is comprised of a plurality of memory cells, each memory cell capable of storing at least two bits per cell.
11. The system of claim 8 , wherein the bit error rate is an outgoing error rate.
12. A method, comprising: determining whether a codeword read from a memory array is correctable using error control coding (ECC) at a first code rate, and if so, performing error correction; if the codeword is not correctable, providing an uncorrectable codeword signal; using the uncorrectable codeword signal to determine an outgoing error rate; and if the outgoing error rate exceeds a predetermined threshold, changing the first code rate to a second code rate by computer.
13. The method of claim 12 , further comprising reading a plurality of codewords encoded at the first code rate out of the memory array, encoding the plurality of codewords using the second code rate, and writing the plurality of codewords encoded at the second code rate back to the memory array.
14. The method of claim 12 , wherein the memory array is an array of NAND flash memory cells.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 8, 2007
February 21, 2012
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