A dielectric film containing a HfO2/ZrO2 nanolaminate and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. A dielectric layer containing a HfO2/ZrO2 nanolaminate may be realized in a wide variety of electronic devices and systems.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic device comprising: a semiconductor substrate; a dielectric film disposed on the semiconductor substrate, the dielectric film containing a nanolaminate, the nanolaminate having an initial layer, the nanolaminate including: a plurality of layers of hafnium oxide, each layer of hafnium oxide essentially consisting of hafnium and oxygen, one of the layers of hafnium oxide being the initial layer; a plurality of layers of zirconium oxide, each layer of zirconium oxide essentially consisting of zirconium and oxygen, wherein between each of the layers of zirconium oxide one of the layers of the plurality of layers of hafnium oxide is disposed; and a transition layer between one of the layers of hafnium oxide and one of the layers of zirconium oxide, the transition layer having a graded composition.
2. The electronic device of claim 1 , wherein the dielectric film is configured essentially as the nanolaminate.
3. The electronic device of claim 1 , wherein the semiconductor substrate includes a non-silicon substrate.
4. The electronic device of claim 1 , wherein the dielectric film is structured essentially as the nanolaminate configured as a gate dielectric of a transistor.
5. The electronic device of claim 1 , wherein the dielectric film is structured essentially as the nanolaminate configured in a memory device.
6. The electronic device of claim 1 , wherein the electronic device has conductive connections to couple a signal from a device in an electronic system to a conductive layer disposed on and contacting the dielectric film.
7. A transistor comprising: a body region between a first source/drain region and a second source/drain region on a silicon substrate; a dielectric film containing a nanolaminate on the body region between the first and second source/drain regions, the nanolaminate having an initial layer, the nanolaminate including: a plurality of layers of hafnium oxide, each layer of hafnium oxide essentially consisting of hafnium and oxygen, one of the layers of hafnium oxide being the initial layer; a plurality of layers of zirconium oxide, each layer of zirconium oxide essentially consisting of zirconium and oxygen, wherein between each of the layers of zirconium oxide one of the layers of the plurality of layers of hafnium oxide is disposed; and a transition layer between one of the layers of hafnium oxide and one of the layers of zirconium oxide, the transition layer having a graded composition; and a gate coupled to the dielectric film.
8. The transistor of claim 7 , wherein each layer of the nanolaminate is formed by atomic layer deposition.
9. The transistor of claim 7 , wherein the nanolaminate includes a final layer opposite the body region, the final layer being one of the plurality of hafnium oxide layers.
10. The transistor of claim 7 , wherein the dielectric film has a dielectric constant in the range from about 10 to about 25.
11. The transistor of claim 7 , wherein the gate is a control gate of the transistor.
12. A transistor comprising: a body region between a first source/drain region and a second source/drain region on a semiconductor substrate; a dielectric film containing a nanolaminate disposed on the body region between the first source/drain region and second source/drain region, the nanolaminate having an initial layer, the nanolaminate including: a plurality of layers of hafnium oxide, each layer of hafnium oxide essentially consisting of hafnium and oxygen, one of the layers of hafnium oxide being the initial layer; a plurality of layers of zirconium oxide, each layer of zirconium oxide essentially consisting of zirconium and oxygen, wherein between each of the layers of zirconium oxide one of the layers of the plurality of layers of hafnium oxide is disposed; and a transition layer between one of the layers of hafnium oxide and one of the layers of zirconium oxide, the transition layer having a graded composition; and a floating gate coupled to the dielectric film; and a control gate separated from the floating gate by an insulator.
13. The transistor of claim 12 , wherein semiconductor substrate includes a silicon-on-sapphire substrate.
14. The transistor of claim 12 , wherein the dielectric film is substantially amorphous.
15. The transistor of claim 12 , wherein the dielectric film exhibits a dielectric constant in the range from about 9 to about 25.
16. The transistor of claim 12 , wherein the dielectric film exhibits an equivalent oxide thickness (t eq ) in the range from about 3 Angstroms to about 12 Angstroms.
17. The transistor of claim 12 , wherein the dielectric film exhibits an equivalent oxide thickness (t eq ) of less than 3 Angstroms.
18. A memory comprising: a number of access transistors, at least one access transistor including a gate coupled to a dielectric film containing a nanolaminate, the dielectric film formed on a body region between a first source/drain region and a second source/drain region on a silicon substrate, the nanolaminate having an initial layer, the nanolaminate including: a plurality of layers of hafnium oxide, each layer of hafnium oxide essentially consisting of hafnium and oxygen, one of the layers of hafnium oxide being the initial layer; a plurality of layers of zirconium oxide, each layer of zirconium oxide essentially consisting of zirconium and oxygen, wherein between each of the layers of zirconium oxide one of the layers of the plurality of layers of hafnium oxide is disposed; and a transition layer between one of the layers of hafnium oxide and one of the layers of zirconium oxide, the transition layer having a graded composition; a number of word lines coupled to a number of the gates of the number of access transistors; a number of source lines coupled to a number of the first source/drain regions of the number of access transistors; and a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors; the dielectric film containing the nanolaminate formed by a method including: forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI 4 precursor; and forming a layer of zirconium oxide on the layer of hafnium oxide.
19. The memory of claim 18 , wherein forming a layer of zirconium oxide includes forming a layer of zirconium oxide by atomic layer deposition.
20. The memory of claim 19 , wherein forming a layer of zirconium oxide by atomic layer deposition includes using a ZrI 4 precursor.
21. The memory of claim 18 , wherein the nanolaminate is substantially amorphous.
22. The memory of claim 18 , wherein the nanolaminate has an equivalent oxide thickness (t eq ) less than 3 Angstroms.
23. A memory comprising: a memory array having a number of access transistors, at least one access transistor including a gate coupled to a dielectric film, the dielectric film disposed on a body region between a first source/drain region and a second source/drain region on a semiconductor substrate, the dielectric film including a nanolaminate, the nanolaminate having an initial layer, the nanolaminate including: a plurality of layers of hafnium oxide, each layer of hafnium oxide essentially consisting of hafnium and oxygen, one of the layers of hafnium oxide being the initial layer; a plurality of layers of zirconium oxide, each layer of zirconium oxide essentially consisting of zirconium and oxygen, wherein between each of the layers of zirconium oxide one of the layers of the plurality of layers of hafnium oxide is disposed; and a transition layer between one of the layers of hafnium oxide and one of the layers of zirconium oxide, the transition layer having a graded composition.
24. The memory of claim 23 , wherein the dielectric film has a dielectric constant in the range from about 9 to about 25.
25. The memory of claim 23 , wherein the dielectric film has an equivalent oxide thickness (t eq ) in the range from about 3 Angstroms to about 12 Angstroms.
26. An electronic system comprising: a processor; a memory, the memory including: a number of access transistors, at least one access transistor having a gate coupled to a dielectric film containing a nanolaminate, the dielectric film containing the nanolaminate formed on a body region between a first source/drain region and a second source/drain region on a silicon substrate, the nanolaminate having an initial layer, the nanolaminate including: a plurality of layers of hafnium oxide, each layer of hafnium oxide essentially consisting of hafnium and oxygen, one of the layers of hafnium oxide being the initial layer; a plurality of layers of zirconium oxide, each layer of zirconium oxide essentially consisting of zirconium and oxygen, wherein between each of the layers of zirconium oxide one of the layers of the plurality of layers of hafnium oxide is disposed; and a transition layer between one of the layers of hafnium oxide and one of the layers of zirconium oxide, the transition layer having a graded composition; and a number of word lines coupled to a number of the gates of the number of access transistors; a number of source lines coupled to a number of the first source/drain regions of the number of access transistors; a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors; and a system bus that couples the processor to the memory; the dielectric film containing the nanolaminate formed by a method including: forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI 4 precursor; and forming a layer of zirconium oxide on the layer of hafnium oxide.
27. The electronic system of claim 26 , wherein forming a layer of zirconium oxide includes forming a layer of zirconium oxide by atomic layer deposition.
28. The electronic system of claim 26 , wherein the dielectric layer is substantially amorphous.
29. An electronic system comprising: a processor; and a memory, the memory including: a number of access transistors, at least one access transistor having a gate coupled to a dielectric film containing a nanolaminate, the film disposed on a body region between a first source/drain region and a second source/drain region on a semiconductor substrate, the nanolaminate having an initial layer, the nanolaminate including: a plurality of layers of hafnium oxide, each layer of hafnium oxide essentially consisting of hafnium and oxygen, one of the layers of hafnium oxide being the initial layer; a plurality of layers of zirconium oxide, each layer of zirconium oxide essentially consisting of zirconium and oxygen, wherein between each of the layers of zirconium oxide one of the layers of the plurality of layers of hafnium oxide is disposed; and a transition layer between one of the layers of hafnium oxide and one of the layers of zirconium oxide, the transition layer having a graded composition; and a system bus that couples the processor to the memory.
30. The electronic system of claim 29 , wherein the electronic system includes an information handling device.
31. The electronic system of claim 29 , wherein the electronic system includes a wireless system.
32. The electronic system of claim 29 , wherein the dielectric film has a dielectric constant in the range from about 9 to about 25.
33. The electronic system of claim 29 , wherein the dielectric film exhibits an equivalent oxide thickness (t eq ) in the range from about 3 Angstroms to about 12 Angstroms.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 11, 2005
February 28, 2012
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