In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus including a memory in a processing system, the apparatus comprising: a random access memory, wherein the random access memory implements a plurality of first in first out (FIFOs); a first interface, coupled to the random access memory, between the random access memory and a plurality of storage devices, wherein the first interface operates in a first in first out (FIFO) manner to write data from one of the plurality of storage devices in the FIFO manner to a FIFO of the plurality of FIFOs, and read data from the FIFO to one of the plurality of storage devices in the FIFO manner; and a second interface, coupled to the random access memory, between the random access memory and a processor, wherein the second interface operates in a random access manner to read data in the random access manner from the FIFO and provide the data to the processor, and write data from the processor in the random access manner to the FIFO.
2. The apparatus of claim 1 , wherein the random access memory includes a static random access memory configured as a data tightly coupled memory.
3. The apparatus of claim 1 , further comprising: a FIFO controller, wherein each of the plurality of FIFOs is associated with a respective one of the plurality of storage devices, and wherein the FIFO controller controls access to the plurality of FIFOs.
4. The apparatus of claim 1 , further comprising: a FIFO controller, wherein each of the plurality of FIFOs is associated with a respective one of the plurality of storage devices, wherein each of the plurality of FIFOs has a configurable size and a configurable base address, and wherein the FIFO controller controls access to the plurality of FIFOs.
5. The apparatus of claim 1 , further comprising: a FIFO controller, wherein each of the plurality of FIFOs is associated with a respective one of the plurality of storage devices, wherein each of the plurality of FIFOs is configurable by a bus interface unit module through the second interface, and wherein the FIFO controller controls access to the plurality of FIFOs.
6. The apparatus of claim 1 , further comprising: a FIFO controller, wherein each of the plurality of FIFOs is associated with a respective one of the plurality of storage devices, wherein each of the plurality of FIFOs has a configurable size and a configurable base address, wherein each of the plurality of FIFOs is configurable by a bus interface unit module through the second interface, and wherein the FIFO controller controls access to the plurality of FIFOs.
7. The apparatus of claim 1 , further comprising: a plurality of FIFO controllers, wherein each of the plurality of FIFO controllers is associated with a respective one of the plurality of FIFOs; and an arbiter circuit coupled between the plurality of FIFO controllers and the random access memory.
8. The apparatus of claim 1 , wherein the second interface is one of a plurality of second interfaces, and wherein the plurality of second interfaces includes: a bus interface unit interface, that operates in the random access manner, between the random access memory and a bus interface unit module.
9. The apparatus of claim 1 , wherein the second interface is one of a plurality of second interfaces, and wherein the plurality of second interfaces includes: a bus interface unit interface, that operates in the random access manner, between the random access memory and a bus interface unit module, wherein the plurality of FIFOs in the random access memory are configurable by the bus interface unit module.
10. The apparatus of claim 1 , wherein the second interface is one of a plurality of second interfaces, and wherein the plurality of second interfaces includes: a first processor interface, that operates in the random access manner, between the random access memory and a first processor; and a second processor interface, that operates in the random access manner, between the random access memory and a second processor.
11. The apparatus of claim 1 , wherein the second interface is one of a plurality of second interfaces, and wherein the plurality of second interfaces includes: a data streamer interface, that operates in the random access manner, between the random access memory and a data streamer.
12. The apparatus of claim 1 , wherein the second interface is one of a plurality of second interfaces, and wherein the plurality of second interfaces includes: a bus interface unit interface, that operates in the random access manner, between the random access memory and a bus interface unit module; a first processor interface, that operates in the random access manner, between the random access memory and a first processor; a second processor interface, that operates in the random access manner, between the random access memory and a second processor; and a data streamer interface, that operates in the random access manner, between the random access memory and a data streamer.
13. A method of operating a memory in a processing system, wherein the memory includes a first interface and a second interface, the method comprising: configuring a plurality of FIFOs (first in first out) in the memory; operating, in a FIFO manner, the first interface between the memory and a plurality of storage devices, wherein operating in the FIFO manner comprises: reading data from one of the plurality of storage devices and providing the data to a FIFO of the plurality of FIFOs in the FIFO manner; and writing data from the FIFO to one of the plurality of storage devices in the FIFO manner; and operating, in a random access manner, the second interface between the memory and a processor, wherein operating in the random access manner comprises: reading data in the random access manner from the FIFO and providing the data to the processor; and receiving data from the processor in the random access manner and storing the data in the FIFO of the plurality of FIFOs.
14. A system for processing data, comprising: a first bus; a second bus; a central processing unit; a dynamic random access memory, wherein the dynamic random access memory implements a plurality of FIFOs; a direct memory access circuit coupled to the dynamic random access memory via the first bus; and a data stream processor, coupled to the central processing unit via the second bus and coupled to the direct memory access circuit, wherein the data stream processor includes a hybrid buffer operation (HBO) circuit that includes: a static random access memory; a first interface, coupled to the static random access memory, between the static random access memory and a plurality of storage devices, wherein the first interface operates in a first in first out (FIFO) manner to write data from one of the plurality of storage devices in the FIFO manner to a FIFO of the plurality of FIFOs, and read data from the FIFO to one of the plurality of storage devices in the FIFO manner; and a second interface, coupled to the static random access memory, between the static random access memory and a processor, wherein the second interface operates in a random access manner to read data in the random access manner from the FIFO and provide the data to the processor, and write data from the processor in the random access manner to the FIFO.
15. The system of claim 14 , further comprising: a pixel processor coupled between the data stream processor and the direct memory access circuit; and a video cache coupled between the data stream processor and the direct memory access circuit.
16. The system of claim 14 , wherein the HBO circuit further comprises: a FIFO controller, wherein each of the plurality of FIFOs is associated with a respective one of the plurality of storage devices.
17. The system of claim 14 , wherein the HBO circuit further comprises: a plurality of FIFO controllers, wherein each of the plurality of FIFOs is associated with a respective one of the plurality of FIFO controllers.
18. The apparatus of claim 14 , further comprising: a plurality of FIFO controllers, wherein each of the plurality of FIFO controllers is associated with a respective one of the plurality of FIFOs; and an arbiter circuit coupled between the plurality of FIFO controllers and the static random access memory.
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July 27, 2009
February 28, 2012
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