Method for generating a clock signal

1. A computer-implemented method of generating a clock signal, the method including executable instructions that when executed by a processor cause the processor to perform the method, the method comprising: synchronizing an internal clock signal to an external clock signal; selecting a first delay amount and a second delay amount from a plurality of delay amounts based on a first frequency of the external clock signal and a second frequency of the external clock signal, respectively, wherein the first delay amount is provided by a first time delay circuit and the second delay amount is provided by a second time delay circuit, the first time delay circuit and the second time delay circuit receiving the internal clock signal, wherein the first delay amount and the second delay amount are different; and delaying the external clock signal by the first delay amount and the second delay amount.

2. The method of claim 1 wherein synchronizing an internal clock signal to an external clock signal comprises locking a delay-locked loop to provide the internal clock signal.

3. The method of claim 1 wherein selecting the first delay amount and the second delay amount comprises selecting the first delay circuit and the second delay circuit from a plurality of delay circuits based on the first and second frequencies of the external clock signal to provide a delayed internal clock signal having a delay relative to the internal clock signal.

4. The method of claim 3 wherein the plurality of delay circuits comprises a plurality of trimmable delay circuits.

5. The method of claim 1 wherein the first delay amount corresponds to the first frequency of the external clock signal and the second delay amount corresponds to the second clock frequency of the external clock signal, wherein the second frequency is less than the first frequency and the second delay amount is greater than the first delay amount.

6. The method of claim 1 wherein selecting the first delay amount and the second delay amount comprises: programming a first latency value indicative of the first frequency of the external clock signal; programming a second latency value indicative of the second frequency of the external clock signal; selecting the first delay amount based on the first latency value; and selecting the second delay amount based on the second latency value.

7. A computer-implemented method of generating a clock signal, the method including executable instructions that when executed by a processor cause the processor to perform the method, the method comprising: enabling one of a plurality of delay circuits based on a clock frequency of an external clock signal from which an internal clock signal is based, wherein the internal clock signal is synchronized with the external clock signal, wherein each of the plurality of delay circuits has a different time delay, the plurality of delay circuits being coupled to receive the internal clock signal and provide an output clock signal as the generated clock signal, the output clock signal having a delay relative to the internal clock signal based on the time delay of the enabled delay circuit.

8. The method of claim 7 wherein the plurality of delay circuits comprises a plurality of trimmable delay circuits.

9. The method of claim 7 wherein enabling one of a plurality of delay circuits comprises programming a value in a register indicative of the clock frequency of the external clock signal.

10. The method of claim 9 wherein programming a value in the register indicative of the clock frequency of the external clock signal comprises programming a value indicative of a delay from when a read command is registered and when data becomes available.

11. A computer-implemented method of generating a clock signal, the method including executable instructions that when executed by a processor cause the processor to perform the method, the method comprising: selecting a first delay circuit and a second delay circuit from a plurality of delay circuits, wherein the first delay circuit is selected according to a first clock frequency of an external clock signal and the second delay circuit is selected according to a second clock frequency of the external clock signal, each delay circuit having a different delay; receiving an internal clock signal at the first delay circuit and at the second delay circuit, wherein the internal clock signal is generated based on the external clock signal, the internal clock signal being synchronized with the external clock signal; and delaying the internal clock signal using the first delay circuit and a second delay circuit to provide the generated clock signal, wherein the first delay circuit delays the internal clock signal by a first delay and the second delay circuit delays the internal clock signal by a second delay.

12. The method of claim 11 wherein the second delay is longer delay than the first delay, the second frequency being lower than the first frequency.

13. The method of claim 11 wherein at least one of the first delay circuit and the second delay circuit is selected according to a delay between registration of a read command availability of a first bit of output data.

14. The method of claim 11 wherein the plurality of delay circuits comprises a plurality of trimmable delay circuits, the delay circuits being trimmed according to a speed grade.

15. A computer-implemented method of generating a clock signal, the method including executable instructions that when executed by a processor cause the processor to perform the method, the method comprising: synchronizing an internal clock signal to an external clock signal; and delaying the internal clock signal by a first delay amount and a second delay amount based on a first frequency and a second frequency of the external clock signal, respectively, wherein the first delay amount is provided by a first time delay circuit and the second delay amount is provided by a second time delay circuit, the first time delay and the second time delay being configured to receive the internal clock signal, wherein the first delay amount and the second delay amount are different.

16. The method of claim 15 wherein delaying the internal clock signal comprises: programming a first column address strobe latency value; programming a second column address strobe latency value; delaying the internal clock signal by the first delay amount based on the first column address strobe latency value; and delaying the internal clock signal by the second delay amount based on the second column address strobe latency value.