A computer system which includes a plurality of threads and a garbage collector that traces memory objects and identifies memory objects according to a three-color abstraction. The computer system also includes two methods of deleting compiled code in a self-modifying multi-threaded computer system. The computer system also utilizes a method of handling links between fragments of code in a self-modifying multi-threaded computer system. The computer system also handles patches between two pieces of code.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of deleting compiled code in a self-modifying multi-threaded computer system, the method comprising: selecting a section of compiled code to be deleted; identifying any patches in the section of compiled code; redirecting any identified patches to other code; and deleting the section of compiled code.
2. A method as claimed in claim 1 , wherein the section of compiled code to be deleted has a range of addresses, the method further comprising: examining a frame of a stack in the computer system; identifying whether the frame contains a return address that is in the range of addresses of the section of compiled code to be deleted; and altering the contents of the frame in the event that the frame contains a return address that is in the range of addresses of the section of compiled code to be deleted.
3. A method of deleting compiled code in a self-modifying multi-threaded computer system, the method comprising: selecting a code buffer to delete, the code buffer having an address; generating a hash of the address of the code buffer; selecting a patch block; identifying whether there is a patch into the code buffer to be deleted; if a patch into the bode buffer is identified, redirecting the identified patch to other code; and deleting the code buffer.
4. A method of handling links between fragments of code in a self-modifying multi-threaded computer system, the method comprising: creating patches between compiled pieces of code; storing information in a patch block about each patch as it is made, each patch block including a from address and a to address; configuring the patch blocks in a from chain and a to chain; selecting a code buffer to delete, the code buffer having an address; generating a hash of the address of the code buffer; selecting a patch block; identifying whether there is a patch into the code buffer to be deleted; if a patch into the code buffer is identified, redirecting the identified patch to other code; selecting a patch from the from chain; generating a hash of the selected patch from the from chain; removing the patch block from the from chain; and deleting the selected code buffer.
5. A system having at least one processor for handling patches between two pieces of code, the processor comprising: a control device having access to glue code and at least one patch; a deleter coupled to the control device; an interpreter coupled to the control device; a compiler coupled to the control device; and a hash table coupled to the control device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 29, 2007
February 28, 2012
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