A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit, comprising: a substrate region; a gate electrode level region formed above the substrate region, the gate electrode level region including at least six linear-shaped conductive structures each formed to extend lengthwise in a first direction, the at least six linear-shaped conductive structures including a first linear-shaped conductive structure including a first gate portion that forms a gate electrode of a first transistor of a first transistor type and a second gate portion that forms a gate electrode of a first transistor of a second transistor type, the first linear-shaped conductive structure also including a non-gate portion that extends in the first direction between the first and second gate portions of the first linear-shaped conductive structure, a second linear-shaped conductive structure including a gate portion that forms a gate electrode of a second transistor of the first transistor type, the second linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the second linear-shaped conductive structure, a third linear-shaped conductive structure including a gate portion that forms a gate electrode of a second transistor of the second transistor type, the third linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the third linear-shaped conductive structure, a fourth linear-shaped conductive structure including a gate portion that forms a gate electrode of a third transistor of the first transistor type, the fourth linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the fourth linear-shaped conductive structure, a fifth linear-shaped conductive structure including a gate portion that forms a gate electrode of a third transistor of the second transistor type, the fifth linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the fifth linear-shaped conductive structure, a sixth linear-shaped conductive structure including a first gate portion that forms a gate electrode of a fourth transistor of the first transistor type and a second gate portion that forms a gate electrode of a fourth transistor of the second transistor type, the sixth linear-shaped conductive structure also including a non-gate portion that extends in the first direction between the first and second gate portions of the sixth linear-shaped conductive structure, wherein the second linear-shaped conductive structure is positioned next to and spaced apart from the first linear-shaped conductive structure, wherein the third linear-shaped conductive structure is positioned next to and spaced apart from the first linear-shaped conductive structure, wherein the fourth linear-shaped conductive structure is positioned next to and spaced apart from the sixth linear-shaped conductive structure, wherein the fifth linear-shaped conductive structure is positioned next to and spaced apart from the sixth linear-shaped conductive structure; a first conductive contacting structure formed to physically connect to the non-gate portion of the second linear-shaped conductive structure, wherein the non-gate portion of the second linear-shaped conductive structure extends the first direction beyond the first conductive contacting structure and away from the gate portion of the second linear-shaped conductive structure by a first extension distance as measured in the first direction; a second conductive contacting structure formed to physically connect to the non-gate portion of the third linear-shaped conductive structure, wherein the non-gate portion of the third linear-shaped conductive structure extends in the first direction beyond the second conductive contacting structure and away from the gate portion of the third linear-shaped conductive structure by a second extension distance as measured in the first direction; a third conductive contacting structure formed to physically connect to the non-gate portion of the fourth linear-shaped conductive structure, wherein the non-gate portion of the fourth linear-shaped conductive structure extends in the first direction beyond the third conductive contacting structure and away from the gate portion of the fourth linear-shaped conductive structure by a third extension distance as measured in the first direction; and a fourth conductive contacting structure formed to physically connect to the non-gate portion of the fifth linear-shaped conductive structure, wherein the non-gate portion of the fifth linear-shaped conductive structure extends in the first direction beyond the fourth conductive contacting structure and away from the gate portion of the fifth linear-shaped conductive structure by a fourth extension distance as measured in the first direction, wherein at least two of the first, second, third, and fourth extension distances are different.
2. An integrated circuit as recited in claim 1 , wherein the at least six linear-shaped conductive structures within the gate electrode level region includes a seventh linear-shaped conductive structure that does not form a gate electrode of a transistor and that is positioned between at least two gate forming linear-shaped conductive structures that each form at least one gate electrode of at least one transistor, wherein a size of the seventh linear-shaped conductive structure as measured in a second direction perpendicular to the first direction is substantially equal to a size of one or more of the at least two gate forming linear-shaped conductive structures as measured in the second direction.
3. An integrated circuit as recited in claim 1 , further comprising: an interconnect level region formed above the substrate region, the interconnect level region including a first linear-shaped conductive interconnect structure formed to extend lengthwise in a second direction perpendicular to the first direction.
4. An integrated circuit as recited in claim 3 , wherein the interconnect level region includes a second linear-shaped conductive interconnect structure formed to extend lengthwise in the second direction, the second linear-shaped conductive interconnect structure is positioned next to and spaced apart from the first linear-shaped conductive interconnect structure.
5. An integrated circuit as recited in claim 4 , wherein each of the second, third, fourth, and fifth linear-shaped conductive structures is positioned between the first and sixth linear-shaped conductive structures in the second direction perpendicular to the first direction.
6. An integrated circuit as recited in claim 1 , wherein the at least six linear-shaped conductive structures within the gate electrode level region includes a seventh linear-shaped conductive structure that does not form a gate electrode of a transistor.
7. An integrated circuit as recited in claim 6 , wherein the at least six linear-shaped conductive structures within the gate electrode level region includes an eighth linear-shaped conductive structure positioned next to and spaced apart from the seventh linear-shaped conductive structure, wherein the eighth linear-shaped conductive structure includes a first gate portion that forms a gate electrode of a fifth transistor of the first transistor type and a second gate portion that forms a gate electrode of a fifth transistor of the second transistor type.
8. An integrated circuit as recited in claim 6 , wherein a size of the seventh linear-shaped conductive structure as measured in a second direction perpendicular to the first direction is substantially equal to a size of a neighboring linear-shaped conductive structure as measured in the second direction, wherein the neighboring linear-shaped conductive structure is positioned next to and spaced apart from the seventh linear-shaped conductive structure.
9. An integrated circuit as recited in claim 1 , further comprising: an interconnect level region formed above the substrate region, the interconnect level region including a first linear-shaped conductive interconnect structure formed to extend lengthwise in the first direction.
10. An integrated circuit as recited in claim 9 , wherein the interconnect level region includes a second linear-shaped conductive interconnect structure formed to extend lengthwise in the first direction, the second linear-shaped conductive interconnect structure positioned next to and spaced apart from the first linear-shaped conductive interconnect structure.
11. An integrated circuit as recited in claim 10 , wherein each of the at least six linear-shaped conductive structures has a lengthwise centerline, the at least six linear-shaped conductive structures positioned according to a first equal centerline-to-centerline pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the at least six linear-shaped conductive structures is an integer multiple of the first equal centerline-to-centerline pitch, and wherein the first and second linear-shaped conductive interconnect structures are positioned in a side-by-side manner according to a second equal centerline-to-centerline pitch as measured in the second direction, the second equal centerline-to-centerline pitch defined as a fractional multiple of the first equal centerline-to-centerline pitch.
12. An integrated circuit as recited in claim 11 , wherein the second equal centerline-to-centerline pitch is less than or equal to the first equal centerline-to-centerline pitch.
13. An integrated circuit as recited in claim 12 , wherein the fractional multiple of the first equal centerline-to-centerline pitch is one.
14. An integrated circuit as recited in claim 13 , wherein the gate electrode level region includes at least one non-gate forming linear-shaped conductive structure that does not form a gate electrode of a transistor.
15. An integrated circuit as recited in claim 1 , wherein each of the at least six linear-shaped conductive structures has a lengthwise centerline, wherein the first, second, fourth, and sixth linear-shaped conductive structures are positioned according to an equal pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the first, second, fourth, and sixth linear-shaped conductive structures is an integer multiple of the equal pitch, and wherein the first, third, fifth, and sixth linear-shaped conductive structures are positioned according to the equal pitch as measured in the second direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the first, third, fifth and sixth linear-shaped conductive structures is an integer multiple of the equal pitch, wherein the second linear-shaped conductive structure is substantially co-aligned with the third linear-shaped conductive structure along a common line of extent in the first direction, and wherein the second linear-shaped conductive structure is separated from the third linear-shaped conductive structure by a first line end spacing distance as measured in the first direction, wherein the fourth linear-shaped conductive structure is substantially co-aligned with the fifth linear-shaped conductive structure along another common line of extent in the first direction, and wherein the fourth linear-shaped conductive structure is separated from the fifth linear-shaped conductive structure by a second line end spacing distance as measured in the first direction.
16. An integrated circuit as recited in claim 15 , wherein the third and fourth linear-shaped conductive structures are electrically connected to each other through one or more conductive structures located within a level of the integrated circuit other than a gate electrode level, wherein the gate electrode level includes the gate electrode level region.
17. An integrated circuit as recited in claim 16 , wherein the third linear-shaped conductive structure is positioned within 360 nanometers of the fourth linear-shaped conductive structure.
18. An integrated circuit as recited in claim 15 , wherein the at least six linear-shaped conductive structures within the gate electrode level region includes a seventh linear-shaped conductive structure that does not form a gate electrode of a transistor, wherein the seventh linear-shaped conductive structure is positioned next to and spaced apart from either the first linear-shaped conductive structure or the sixth linear-shaped conductive structure.
19. An integrated circuit as recited in claim 18 , wherein the at least six linear-shaped conductive structures within the gate electrode level region includes an eighth linear-shaped conductive structure positioned next to and spaced apart from the seventh linear-shaped conductive structure, wherein the eighth linear-shaped conductive structure includes a first gate portion that forms a gate electrode of a fifth transistor of the first transistor type and a second gate portion that forms a gate electrode of a fifth transistor of the second transistor type.
20. An integrated circuit as recited in claim 18 , wherein a size of the seventh linear-shaped conductive structure as measured in a second direction perpendicular to the first direction is substantially equal to a size of a neighboring linear-shaped conductive structure as measured in the second direction, wherein the neighboring linear-shaped conductive structure is positioned next to and spaced apart from the seventh linear-shaped conductive structure.
21. An integrated circuit as recited in claim 15 , wherein the first line end spacing distance is less than or equal to 240 nanometers.
22. An integrated circuit as recited in claim 21 , wherein the second line end spacing distance is less than or equal to 240 nanometers.
23. An integrated circuit as recited in claim 22 , wherein each of the second and third transistors of the first transistor type is formed in part by a shared diffusion region of a first diffusion type, wherein each of the second and third transistors of the second transistor type is formed in part by a shared diffusion region of a second diffusion type, and wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type.
24. An integrated circuit as recited in claim 23 , further comprising: a plurality of interconnect levels each including a number of conductive interconnect structures, wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type through a first linear-shaped conductive interconnect structure formed to extend lengthwise in the second direction within a first interconnect level of the plurality of interconnect levels.
25. An integrated circuit as recited in claim 24 , wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type through a second linear-shaped conductive interconnect structure formed to extend lengthwise in the first direction within a second interconnect level of the plurality of interconnect levels.
26. An integrated circuit as recited in claim 15 , wherein two of the second, third, fourth, and fifth linear-shaped conductive structures have different lengths as measured in the first direction.
27. An integrated circuit as recited in claim 26 , wherein each of the first and sixth linear-shaped conductive structures has a respective end aligned to a first position in the first direction, and wherein two of the second, third, fourth, and fifth linear-shaped conductive structures each has a respective end, aligned to the first position in the first direction.
28. An integrated circuit as recited in claim 27 , wherein each of the second, third, fourth, and fifth linear-shaped conductive structures is positioned between the first and sixth linear-shaped conductive structures in the second direction perpendicular to the first direction.
29. An integrated circuit as recited in claim 27 , wherein the at least six linear-shaped conductive structures within the gate electrode level region includes a seventh linear-shaped conductive structure that does not form a gate electrode of a transistor.
30. An integrated circuit as recited in claim 29 , wherein the seventh linear-shaped conductive structure is positioned next to and spaced apart from either the first linear-shaped conductive structure or the sixth linear-shaped conductive structure.
31. An integrated circuit as recited in claim 30 , wherein the at least six linear-shaped conductive structures within the gate electrode level region includes an eighth linear-shaped conductive structure positioned next to and spaced apart from the seventh linear-shaped conductive structure, wherein the eighth linear-shaped conductive structure includes a first gate portion that forms a gate electrode of a fifth transistor of the first transistor type and a second gate portion that forms a gate electrode of a fifth transistor of the second transistor type.
32. An integrated circuit as recited in claim 15 , wherein three of the second, third, fourth, and fifth linear-shaped conductive structures have different lengths as measured in the first direction.
33. An integrated circuit as recited in claim 32 , wherein each of the first and sixth linear-shaped conductive structures has a respective end aligned to a first position in the first direction, and wherein two of the second, third, fourth, and fifth linear-shaped conductive structures each has a respective end aligned to the first position in the first direction.
34. An integrated circuit as recited in claim 33 , wherein each of the second, third, fourth, and fifth linear-shaped conductive structures is positioned between the first and sixth linear-shaped conductive structures in the second direction perpendicular to the first direction.
35. An integrated circuit as recited in claim 33 , wherein the at least six linear-shaped conductive structures within the gate electrode level region includes a seventh linear-shaped conductive structure that does not form a gate electrode of a transistor.
36. An integrated circuit as recited in claim 35 , wherein the seventh linear-shaped conductive structure is positioned next to and spaced apart from either the first linear-shaped conductive structure or the sixth linear-shaped conductive structure.
37. An integrated circuit as recited in claim 36 , wherein the at least six linear-shaped conductive structures within the gate electrode level region includes an eighth linear-shaped conductive structure positioned next to and spaced apart from the seventh linear-shaped conductive structure, wherein the eighth linear-shaped conductive structure includes a first gate portion that forms a gate electrode of a fifth transistor of the first transistor type and a second gate portion that forms a gate electrode of a fifth transistor of the second transistor type.
38. An integrated circuit as recited in claim 15 , wherein the first conductive contacting structure is positioned a first connection distance away from the gate portion of the second linear-shaped conductive structure as measured in the first direction, wherein the second conductive contacting structure is positioned a second connection distance away from the gate portion of the third linear-shaped conductive structure as measured in the first direction, wherein the third conductive contacting structure is positioned a third connection distance away from the gate portion of the fourth linear-shaped conductive structure as measured in the first direction, wherein the fourth conductive contacting structure is positioned a fourth connection distance away from the gate portion of the fifth linear-shaped conductive structure as measured in the first direction, and wherein at least two of the first, second, third, and fourth connection distances are different.
39. An integrated circuit as recited in claim 38 , wherein two of the second, third, fourth, and fifth linear-shaped conductive structures have different lengths as measured in the first direction.
40. An integrated circuit as recited in claim 39 , wherein each of the second, third, fourth, and fifth linear-shaped conductive structures is positioned between the first and sixth linear-shaped conductive structures in the second direction perpendicular to the first direction.
41. An integrated circuit as recited in claim 39 , wherein the third linear-shaped conductive structure is electrically connected to the fourth linear-shaped conductive structure through one or more conductive structures located within a level of the integrated circuit other than a gate electrode level, wherein the gate electrode level includes the gate electrode level region.
42. An integrated circuit as recited in claim 41 , wherein the at least six linear-shaped conductive structures within the gate electrode level region includes a seventh linear-shaped conductive structure that does not form a gate electrode of a transistor.
43. An integrated circuit as recited in claim 38 , wherein at least three of the first, second, third, and fourth connection distances are different.
44. An integrated circuit as recited in claim 43 , wherein two of the second, third, fourth, and fifth linear-shaped conductive structures have different lengths as measured in the first direction.
45. An integrated circuit as recited in claim 44 , wherein each of the second, third, fourth, and fifth linear-shaped conductive structures is positioned between the first and sixth linear-shaped conductive structures in the second direction perpendicular to the first direction.
46. An integrated circuit as recited in claim 44 , wherein the at least six linear-shaped conductive structures within the gate electrode level region includes a seventh linear-shaped conductive structure that does not form a gate electrode of a transistor.
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October 1, 2009
March 6, 2012
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