Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method, in a data processing system, for tracking effective addresses through a processor pipeline of the data processing system, the method comprising: fetching an instruction from an instruction cache; associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction; associating, by the effective address table logic, an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset identifying the fetched instruction in association with the entry in the EAT, wherein the eatag offset is an offset from the base eatag; and processing the instruction through the processor pipeline utilizing the EAT by processing the eatag.
2. The method of claim 1 , wherein: the entry in the EAT is associated with a plurality of instructions in a group of instructions, the entry in the EAT is created in response to a fetch of a first instruction in the group of instructions from a new cache line of the instruction cache of the data processing system, and the entry in the EAT is updated as additional instructions are fetched from the cache line.
3. The method of claim 2 , wherein updating of the entry in the EAT as additional instructions are fetched from the cache line is discontinued in response to a fetched instruction in the group of instructions being a taken branch instruction or an instruction being fetched from another cache line in the instruction cache of the data processing system.
4. The method of claim 1 , wherein the instruction is fetched as part of an instruction fetch group fetched from an instruction cache, and wherein all of the instructions in the instruction fetch group have a same base eatag but have different eatag offsets, and wherein the base eatag is sent to an instruction dispatch unit where it is stored in an instruction buffer with the instructions of the instruction fetch group fetched from the instruction cache.
5. The method of claim 4 , further comprising: grouping instructions in the instruction buffer into at least one global completion table (GCT) instruction group; calculating a set of eatags for each GCT instruction group, the set of eatags comprising a plurality of base eatags; calculating, for each GCT instruction group, and for each effective address range associated with the GCT instruction group, a count of a number of instructions from the base eatag included in the GCT instruction group; and providing the set of eatags and the count of a number of instructions for each effective address range of the GCT instruction group to an instruction sequencer unit along with the instructions in the GCT instruction group.
6. The method of claim 5 , further comprising, for each global completion table instruction group: calculating, in the instruction sequencer unit, a plurality of calculated eatags corresponding to a first instruction in the GCT instruction group and at least one of an eatag of a last instruction in the GCT instruction group or an eatag of a branch instruction in the GCT instruction group, based on a set of eatags and count of number of instructions for each effective address range associated with the GCT instruction group; placing the calculated eatags into at least one instruction queue; and storing the calculated eatags in a global completion table in association with the GCT instruction group.
7. The method of claim 6 , further comprising: in response to a flush, sending an eatag of an oldest instruction in a GCT instruction group associated with an instruction causing the flush to the effective address table logic; and determining an EAT head pointer and restoring branch prediction structures based on the eatag of the oldest instruction.
8. The method of claim 7 , further comprising: in response to multiple flushes occurring, using eatags of instructions causing the flushes to identify one or more younger flush instructions; and invalidating flushes associated with the one or more younger flush instructions.
9. The method of claim 6 , further comprising: sending an eatag of a youngest instruction in the GCT instruction group in response to all instructions in the GCT instruction group completing; and calculating a current instruction based on the eatag of the youngest instruction in the GCT instruction group.
10. The method of claim 1 , wherein each entry in the EAT comprises a base effective address, a first instruction identifier, a last instruction identifier, a closed identifier, a global history vector field, a link stack pointer field, and a branch taken identifier.
11. A data processing system, comprising: a processor pipeline; an instruction cache coupled to the processor pipeline; and effective address table logic coupled to the processor pipeline, wherein: instruction fetching logic of the processor pipeline fetches an instruction from the instruction cache, the effective address table logic associates an entry in an effective address table (EAT) data structure with the fetched instruction, the effective address table logic associates an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset identifying the fetched instruction in association with the entry in the EAT, wherein the eatag offset is an offset from the base eatag, and the processor pipeline processes the instruction utilizing the EAT by processing the eatag.
12. The system of claim 11 , wherein: the entry in the EAT is associated with a plurality of instructions in a group of instructions, the entry in the EAT is created in response to a fetch of a first instruction in the group of instructions from a new cache line of the instruction cache of the data processing system, and the entry in the EAT is updated as additional instructions are fetched from the cache line.
13. The system of claim 12 , wherein updating of the entry in the EAT as additional instructions are fetched from the cache line is discontinued in response to a fetched instruction in the group of instructions being a taken branch instruction or an instruction being fetched from another cache line in the instruction cache of the data processing system.
14. The system of claim 11 , wherein the instruction is fetched as part of an instruction fetch group fetched from an instruction cache, and wherein all of the instructions in the instruction fetch group have a same base eatag but have different eatag offsets, and wherein the base eatag is sent to an instruction dispatch unit where it is stored in an instruction buffer with the instructions of the instruction fetch group fetched from the instruction cache.
15. The system of claim 14 , further comprising: an instruction dispatcher unit; an instruction buffer coupled to the instruction dispatcher unit; and an instruction sequencer unit coupled to the instruction dispatch unit, wherein the instruction dispatch unit: groups instructions in the instruction buffer into at least one global completion table (GCT) instruction group, calculates a set of eatags for each GCT instruction group, the set of eatags comprising a plurality of base eatags, calculates, for each GCT instruction group, and for each effective address range associated with the GCT instruction group, a count of a number of instructions from the base eatag included in the GCT instruction group, and provides the set of eatags and the count of a number of instructions for each effective address range of the GCT instruction group to the instruction sequencer unit along with the instructions in the GCT instruction group.
16. The system of claim 15 , wherein, for each global completion table instruction group: the instruction sequencer unit calculates a plurality of calculated eatags corresponding to a first instruction in the GCT instruction group and at least one of an eatag of a last instruction in the GCT instruction group or an eatag of a branch instruction in the GCT instruction group, based on a set of eatags and count of number of instructions for each effective address range associated with the GCT instruction group, the instruction sequencer unit places the calculated eatags into at least one instruction queue, and the instruction sequencer unit stores the calculated eatags in a global completion table in association with the GCT instruction group.
17. The system of claim 16 , wherein, in response to a flush: the instruction sequencer unit sends an eatag of an oldest instruction in a GCT instruction group associated with an instruction causing the flush to the effective address table logic, and the effective address table logic determines an EAT head pointer and restores branch prediction structures based on the eatag of the oldest instruction.
18. The system of claim 17 , further comprising: eatag age filtering logic coupled to the instruction sequencer unit, wherein, in response to multiple flushes occurring, the eatag age filtering logic filters eatags of instructions causing the flushes to identify one or more younger flush instructions and flushes associated with the one or more younger flush instructions are invalidated.
19. The system of claim 16 , wherein the instruction sequencer unit sends an eatag of a youngest instruction in the GCT instruction group in response to all instructions in the GCT instruction group completing, and wherein a current instruction is calculated based on the eatag of the youngest instruction in the GCT instruction group.
20. The system of claim 11 , wherein each entry in the EAT comprises a base effective address, a first instruction identifier, a last instruction identifier, a closed identifier, a global history vector field, a link stack pointer field, and a branch taken identifier.
21. The method of claim 1 , wherein: the entry in the EAT data structure comprises a base effective address of the instruction fetched from the instruction cache which specifies a beginning memory location of a set of one or more instructions comprising the instruction fetched from the instruction cache, the effective address of the instruction is not passed between stages of the processor pipeline, and the effective address of the instruction is tracked by passing the eatag through the processor pipeline and utilizing the EAT based on the eatag.
22. The system of claim 11 , wherein: the entry in the EAT data structure comprises a base effective address of the instruction fetched from the instruction cache which specifies a beginning memory location of a set of one or more instructions comprising the instruction fetched from the instruction cache, the effective address of the instruction is not passed between stages of the processor pipeline, and the effective address of the instruction is tracked by passing the eatag through the processor pipeline and utilizing the EAT based on the eatag.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 13, 2009
March 6, 2012
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.