A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A molded leadless packaged semiconductor multichip module comprising: first and second pairs of mosfets wherein each mosfet having a source, a drain and a gate; electrically insulating molding compound encapsulating the mosfets; three source clips, wherein one of the source clips is directly connected to two sources of two of the mosfets, respectively, and each of the other two source clips is directly connected to one of the other two sources, respectively, of the other two mosfets; four gate clips, each gate clip directly connected to the gate of one of the mosfets, respectively; two drain clips, each drain clip directly connected to a different pair of the mosfets; a plurality of leadless contacts exposed from the encapsulating compound and disposed in a common plane of one surface of the module for making electrical contact to the sources, gates and drains of the mosfets.
2. The molded leadless packaged semiconductor multichip module of claim 1 wherein the mosfets and arranged in a two by two array.
3. The molded leadless packaged semiconductor multichip module of claim 1 wherein the leadless contacts for at least the sources and drains are arranged in first and second linear arrays on opposite edges of the module.
4. The molded leadless packaged semiconductor multichip module of claim 3 wherein the leadless contacts for the gates are arranged in the same arrays as the source and drain contacts.
5. The molded leadless packaged semiconductor multichip module of claim 3 wherein the leadless contacts for the gates are arranged in along the edges transverse to the edges holding the source and drain arrays of contacts.
6. The molded leadless packaged semiconductor multichip module of claim 5 wherein the gate contacts are at the ends of the respective arrays.
7. The molded leadless packaged semiconductor multichip module of claim 5 wherein the gate contacts are proximate the centers of the respective arrays.
8. The molded leadless packaged semiconductor multichip module of claim 1 wherein the mosfets comprise two n-channel mosfets and two p-channel mosfets.
9. The molded leadless packaged semiconductor multichip module of claim 1 wherein the four mosfets comprise two p-channel mosfets and two n-channel mosfets.
10. The molded leadless packaged semiconductor multichip module of claim 9 wherein the p-channel drains are connected to one drain clip and the n-channel drains are connected to the other drain clip.
11. The molded molded leadless packaged semiconductor multichip module of claim 10 wherein one of the source clips is directly connected to the n-channel mosfets.
12. A molded leadless packaged semiconductor multichip module comprising: first and second pairs of mosfets wherein each mosfet having a source, a drain and a gate; electrically insulating molding compound encapsulating the mosfets; three source clips, wherein one of the source clips is directly connected to two sources of two of the mosfets, respectively, and each of the other two source clips is directly connected to one of the other two sources, respectively, of the other two mosfets; four gate clips, each gate clip directly connected to the gate of one of the mosfets, respectively; two drain clips, each drain clip directly connected to a different pair of the mosfets; a first array of source heat sinks directly contacting the source clips and at least partially exposed from the encapsulating compound for transferring heat from the sources and the source clips to the ambient environment of the module, and a second array of drain heat sinks directly contacting the drain clips and at least partially exposed from the encapsulating compound for transferring heat from the drains and the drain clip to the ambient environment; and a plurality of leadless contacts exposed from the encapsulating compound and disposed in a common plane of one surface of the module for making electrical contact to the sources, gates and drains of the mosfets.
13. The molded leadless packaged semiconductor multichip module of claim 12 wherein the mosfets are arranged in a two by two array.
14. The molded leadless packaged semiconductor multichip module of claim 12 wherein the leadless contacts for at least the sources and drains are arranged in first and second linear arrays on opposite edges of the module.
15. The molded leadless packaged semiconductor multichip module of claim 14 wherein the leadless contacts for the gates are arranged in the same arrays as the source and drain contacts.
16. The molded leadless packaged semiconductor multichip module of claim 14 wherein the leadless contacts for the gates are arranged along the edges transverse to the edges holding the source and drain arrays of contacts.
17. The molded leadless packaged semiconductor multichip module of claim 16 wherein the gate contacts are at the ends of the respective arrays.
18. The molded leadless packaged semiconductor multichip module of claim 16 wherein the gate contacts are proximate the centers of the respective arrays.
19. The molded leadless packaged semiconductor multichip module of claim 12 wherein the mosfets comprise two n-channel mosfets and two p-channel mosfets.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 28, 2008
March 20, 2012
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