A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device comprising: a substrate having first and second device regions; first metal silicide contacts in the first device region, the first metal silicide contacts comprise a first metal silicide layer; and second metal silicide contacts in the second device region which are different than the first metal silicide contacts, the second metal silicide contacts comprise a second metal silicide contact layer over the first metal silicide layer.
2. The device of claim 1 comprises: first transistors in the first device region, wherein the first metal silicide contacts are contacts of the first transistors; and second transistors in the second device region, wherein the second metal silicide contacts are contacts of the second transistors.
3. The device of claim 2 wherein the first and second transistors comprise n-type transistors.
4. The device of claim 2 wherein: the first transistors comprise iso transistors and the second transistors comprise nested transistors.
5. The device of claim 1 wherein the second metal silicide contacts comprise a target thickness.
6. The device of claim 4 wherein the second metal silicide contact stacks comprise a target thickness, the target thickness results in R s of the first transistors and R s of the second transistors being about the same.
7. The device of claim 5 wherein the target thickness results in a target R s .
8. A device comprising: a substrate having first and second regions; a first transistor in the first region, the first transistor include first metal silcide contacts, the first metal silicide contacts comprise a first metal silicide layer; a second transistor in the second region, the second transistor includes second metal silicide contacts in the second region; the second metal silicide contacts, which are different from the first metal silicide contacts, comprise a second metal silicide contact layer over the first metal silicide contact layer.
9. The device of claim 8 wherein the first and second transistors comprise n-type transistors.
10. The device of claim 8 wherein the second metal silicide contacts comprise a target thickness.
11. The device of claim 10 wherein the target thickness results in a target R s of the second transistor being about the same as that of the first transistor.
12. An IC comprising: a substrate having first and second regions; first transistors in the first region, wherein the first transistors include first metal silicide contacts; second transistors in the second region, wherein the second transistors include second metal silicide contacts, which are different than the first metal silicide contacts, the second metal silicide contacts comprise more metal silicide layers than the first metal silicide contacts.
13. The IC of claim 12 wherein the second metal silicide contacts comprise a target thickness to result in the first and second transistors having about the same R s .
14. The IC of claim 12 wherein the transistors comprise n-type transistors.
15. The IC of claim 12 wherein: the first transistors comprise iso transistors and the second transistors comprise nested transistors.
16. The IC of claim 15 wherein the second metal silicide contacts comprise a target thickness to result in the first and second transistors having about the same R s .
17. The IC of claim 15 wherein the first and second transistors are n-type transistors.
18. The device in claim 12 wherein: the first metal silicide contacts comprise a first metal silicide layer; and the second metal silicide contacts comprise a second metal silicide layer over the first metal silicide layer.
19. The IC in claim 18 wherein the first and second metal silicide layers are of the same type of metal silicide layers.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 2, 2010
March 27, 2012
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