The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a central processing unit; a rewritable nonvolatile memory targeted for access by the central processing unit, wherein the nonvolatile memory includes a memory array, and a plurality of electrically rewritable nonvolatile storage devices each having a select terminal connected with a select control line and a data terminal connected with a data line, wherein one pair of the storage devices sharing the select control line can form a twin cell, a first read circuit for differentially amplifying complementary data read out to different data lines from a pair of storage devices of the twin cell selected by the select control line, a second read circuit for amplifying data read out from one storage device of the selected twin cell, a write control circuit, an external interface circuit, wherein the write control circuit has a write mode for forcing a pair of storage devices of the selected twin cell to hold non-inverted data and inverted data of write data of one bit, wherein the external interface circuit has a first read mode for outputting data resulting from differential amplification of non-inverted data and inverted data read out from a pair of storage devices of the selected twin cell by the first read circuit to outside, and a second read mode for outputting data resulting from amplification of data read out from one storage device of the selected twin cell by the second read circuit to the outside.
2. The semiconductor device of claim 1 , wherein the external interface circuit has a first external interface circuit performing a read operation in the first read mode, and a second external interface circuit performing a read operation in the second read mode.
3. The semiconductor device of claim 2 , further comprising: a first bus connected with the first external interface circuit; a second bus connected with the second external interface circuit; and a bus interface circuit connected with the first and second buses, wherein the first bus is connected with the central processing unit, and wherein, when responding to a request for read access from the central processing unit, the bus interface circuit assigns the first read mode for the first external interface circuit or the second read mode for the second external interface circuit according to an address targeted for the access.
4. The semiconductor device of claim 3 , wherein, when responding to a request for read access from the central processing unit, the bus interface circuit assigns the first read mode for the first external interface circuit or the second read mode for the second external interface circuit according to an address targeted for the access if a mode register is in a first state, and assigns the first read mode for the first external interface circuit regardless of the address targeted for the access if the mode register is in a second state.
5. A semiconductor device comprising: a central processing unit; a rewritable nonvolatile memory targeted for access by the central processing unit, wherein the nonvolatile memory includes: a memory array having a plurality of 1-bit twin cells, each composed of rewritable nonvolatile first and second storage devices, a first read circuit for differentially amplifying complementary data read out from both storage devices of the twin cell selected for read, a second read circuit for amplifying data read out from one storage device of the twin cell selected for read, a write control circuit, and an external interface circuit, wherein the write control circuit has a write mode for forcing a pair of storage devices of the selected twin cell to hold non-inverted data and inverted data of write data of one bit, and wherein the external interface circuit has a secure read mode for outputting data resulting from differential amplification of non-inverted data and inverted data read out from a pair of storage devices of the selected twin cell by the first read circuit to outside, and a non-secure read mode for outputting data resulting from amplification of data read out from one storage device of the selected twin cell by the second read circuit to the outside.
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May 3, 2011
March 27, 2012
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