In a high-precision signal detection apparatus and method for a high-speed receiver, signal detection occurs asynchronously of the incoming data. A comparison clock is generated by an oscillator whose effective capacitance is varied by a second, lower speed oscillator connected to the capacitance. This prevents the asynchronous sampling that occurs in a zero-crossing position in the incoming data from remaining in that position in subsequent sampling cycles, so that a valid signal is not missed by the detector.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of operating a receiver, said method comprising: maintaining said receiver in a low-power mode; detecting a received signal having a signal amplitude and a signal frequency, said detecting comprising: comparing said signal amplitude to a threshold to generate a comparison signal, said comparison signal having a first amplitude when said signal amplitude exceeds said threshold and a second amplitude when said signal amplitude fails to exceed said threshold, generating a sampling clock having a sampling frequency that varies during operation of said sampling clock, sampling said comparison signal at intervals determined by said sampling frequency, and outputting a detection signal when said sampled comparison signal has said first amplitude, wherein: variation of said sampling frequency prevents detection failures resulting from repeated sampling of said comparison signal in a region thereof wherein said signal amplitude fails to exceed said threshold; and signaling activation of said receiver responsive to said detection signal.
2. The method of claim 1 wherein said maintaining said receiver in a low-power mode comprises maintaining said receiver in a power-off state.
3. The method of claim 1 wherein said generating a sampling clock comprises: generating a modulating clock signal; using said modulating clock signal to vary an effective capacitance in an oscillator; and generating said sampling clock using said oscillator having said varying capacitance.
4. The method of claim 1 wherein: said comparing comprises subtracting said threshold from said signal amplitude to form a first difference signal; and said sampling comprises sampling said first difference signal.
5. The method of claim 4 wherein: said comparing further comprises subtracting said threshold from an inverse of said signal amplitude to form a second difference signal; and said sampling further comprises: sampling said second difference signal, and combining results of said sampling said first difference signal and said sampling said second difference signal.
6. The method of claim 1 further comprising elongating duration of said detection signal.
7. The method of claim 1 further comprising generating said threshold.
8. The method of claim 7 wherein: said received signal is a differential signal having a received common mode voltage; and said generating said threshold comprises generating a differential threshold signal having a threshold common mode voltage substantially equal to said received common mode voltage.
9. A system comprising: receiver means; and signal detector means for detecting a received signal having a signal amplitude and a signal frequency, said signal detector means comprising: means for comparing said signal amplitude to a threshold to generate a comparison signal, said comparison signal having a first amplitude when said signal amplitude exceeds said threshold and a second amplitude when said signal amplitude fails to exceed said threshold; means for generating a sampling clock having a sampling frequency that varies during operation of said means for generating; means for sampling said comparison signal at intervals determined by said sampling frequency; and means for outputting a detection signal when said sampled comparison signal has said first amplitude; wherein: said receiver means has a low-power mode and activates from said low-power mode responsive to said detection signal; and variation of said sampling frequency prevents detection failures resulting from repeated sampling of said comparison signal in a region thereof wherein said signal amplitude fails to exceed said threshold.
10. The system of claim 9 wherein said low-power mode is a power-off state.
11. The system of claim 9 wherein: said means for generating a sampling clock comprises: means for generating a modulating clock signal, and oscillator means including an effective capacitance; output of said means for generating a modulating clock signal is operatively connected to said effective capacitance to modulate said effective capacitance; and said oscillator means generates said sampling clock.
12. The system of claim 11 wherein: said oscillator means comprises ring oscillator means having stages, each of said stages including resistance means and capacitance means; and said capacitance means comprises: first capacitor means connected between said resistance means and a fixed voltage, and second capacitor means connected between said resistance means and output of said modulating clock signal generating means; whereby: variation of said modulating clock signal output varies effective capacitance of said second capacitor means, thereby varying effective capacitance of said capacitance means, thereby varying said sampling clock.
13. A system comprising: a receiver; and a signal detector for detecting a received signal having a signal amplitude and a signal frequency, said signal detector comprising: a comparison signal generator that compares said signal amplitude to a threshold to generate a comparison signal, said comparison signal having a first amplitude when said signal amplitude exceeds said threshold and a second amplitude when said signal amplitude fails to exceed said threshold, a sampling clock generator that generates a sampling clock having a sampling frequency that varies during operation of said sampling clock generator, a sampler that samples said comparison signal at intervals determined by said sampling frequency; and an output circuit that outputs a detection signal when said sampled comparison signal has said first amplitude; Wherein: said receiver has a low-power mode and activates from said low-power mode responsive to said detection signal; and variation of said sampling frequency prevents detection failures resulting from repeated sampling of said comparison signal in a region thereof wherein said signal amplitude fails to exceed said threshold.
14. The system of claim 13 wherein said low-power mode is a power-off state.
15. The system of claim 13 wherein: said sampling clock generator comprises: a modulating clock signal generator, and an oscillator including an effective capacitance; output of said modulating clock signal generator is operatively connected to said effective capacitance to modulate said effective capacitance; and said oscillator generates said sampling clock.
16. The system of claim 15 wherein: said oscillator comprises a ring oscillator having stages, each of said stages including resistance and capacitance; and said capacitance comprises: a first capacitor connected between said resistance and a fixed voltage, and a second capacitor connected between said resistance and output of said modulating clock signal generator; whereby: variation of said modulating clock signal output varies effective capacitance of said second capacitor, thereby varying effective capacitance of said capacitance, thereby varying said sampling clock.
17. The system of claim 13 wherein: said comparison signal generator comprises a first subtractor that subtracts said threshold from said signal amplitude to form a first difference signal; and said sampler samples said first difference signal.
18. The system of claim 17 wherein: said comparison signal generator further comprises a second subtractor that subtracts said threshold from an inverse of said signal amplitude to form a second difference signal; and said sampler also samples said second difference signal, and comprises a combinatorial function that combines results of said sampling said first difference signal and said sampling said second difference signal.
19. The system of claim 13 further comprising a pulse stretcher for elongating duration of said detection signal.
20. The system of claim 13 further comprising a threshold generator for generating said threshold; wherein: said received signal is a differential signal having a received common mode voltage; and said threshold generator comprises a differential threshold signal generator that generates a threshold signal having a threshold common mode voltage substantially equal to said received common mode voltage.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 13, 2011
March 27, 2012
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