A radio frequency identification (RFID) device includes an antenna linked to a receiving circuit, the antenna tuned to receive a radio frequency (RF) time-code signal from a public source, a controller circuit and an internal clock linked to the receiving circuit, a microcontroller linked to the receiving circuit, a memory linked to the microcontroller, and a battery linked to and powering the receiving circuit, controller circuit, internal clock, microcontroller and memory.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A system comprising: a radio frequency identification (RFID) device comprising: an antenna tuned to receive a radio frequency (RF) position signal from a public source; a receiving circuit linked to the antenna, wherein the receiving circuit is configured to convert the received RF position signal into a digital position bit stream; a controller circuit linked to the receiving circuit, wherein the controller circuit is configured to decode the digital position bit stream; and an internal clock linked to the controller circuit, wherein a time maintained by the internal clock is updated based on the decoded position bit stream received from the controller circuit.
2. The system of claim 1 , further comprising: an RFID interrogator configured to interrogate the RFID device and receive in response an RFID identification and a time stamp, wherein the time stamp corresponds to the time maintained by the internal clock.
3. The system of claim 2 , further comprising: a subsystem linked to the RFID interrogator, wherein the subsystem is configured to store the RFID identification and the time stamp.
4. A system comprising: a radio frequency identification (RFID) device comprising: an antenna tuned to receive a global positioning system (GPS) speed signal from a public source; a receiving circuit linked to the antenna, wherein the receiving circuit is configured to convert the received GPS speed signal into a digital speed bit stream; a controller circuit linked to the receiving circuit, wherein the controller circuit is configured to decode the digital speed bit stream; and an internal clock linked to the controller circuit, wherein a time maintained by the internal clock is updated based on the decoded speed bit stream received from the controller circuit.
5. The system of claim 4 , further comprising: an RFID interrogator configured to interrogate the RFID device and receive in response an RFID identification and a time stamp, wherein the time stamp corresponds to the time maintained by the internal clock.
6. The system of claim 5 , further comprising: a subsystem linked to the RFID interrogator, wherein the subsystem is configured to store the RFID identification and the time stamp.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 14, 2011
April 10, 2012
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