Adaptive data prefetch

1. A method of operating a data processing system having a processor, a unit that includes a first level cache and additional n levels of cache, a prefetch system and a memory, n being an integer greater than or equal to 0, the unit being operable to store lines of data in the first level cache, the first level cache being operable to store an integer w lines of data, the memory being operable to store an integer z lines of data, the unit being operable to store lines of data in the additional n levels of cache, each of additional 1:n levels of cache being operable to store integer x 1:n lines of data, respectively, w<x 1 < . . . <x x-1 <x n <z, the processor being operable to access a line of data in the first level cache within a time t f , the processor being operable to access a line of data in each of the additional 1:n levels of cache within time t 1:n , respectively, t 0 <t 1 < . . . <t n-1 <t n , the processor being operable to access a line of data in the memory within a time t m , t f <t 1 < . . . <t n-1 <t n <t m , the prefetch system being operable to retrieve up to y n lines of data from the memory and to store the up to y n lines of data in the n level cache, the prefetch system being operable to retrieve up to y f lines of data from one of the memory and 1:n levels of cache and to store the up to y f lines of data in the first level cache, said method comprising: running the data processing system in a first mode; determining whether a second mode is required; and running the data processing system in the second mode, wherein in the first mode, the prefetch system is enabled to: retrieve y f lines of data from one of the memory and the 1:n level caches and to store the y f lines of data in the first level cache, retrieve y n lines of data from the memory and store the y n lines of data in the n level cache, and enable store prefetching via stream filtering, wherein the second mode is at least one of a low-power mode or a medium-power mode, wherein in the low-power mode the prefetch system is enabled to: retrieve b lines of data from one of the memory and the 1:n level caches and store the b lines of data in the first level cache, wherein b<y f , retrieve a lines of data from the memory and store the a lines of data in the n level cache, wherein a<y n , and disable store prefetching via stream filtering thereby reducing power consumption by the data processing system, and wherein in the medium-power mode the prefetch system is enabled to: disable prefetching into the first level cache, retrieve the a lines of data from the memory and store the a lines of data in the n level cache, wherein a<y n , and disable store prefetching via stream filtering thereby reducing power consumption by the data processing system.

2. The method of claim 1 , wherein said determining whether a second mode is required comprises monitoring a workload characteristic of the data processing system.

3. The method of claim 2 , wherein said monitoring a workload characteristic of the data processing system comprises monitoring at least one of a number of data store requests into the memory, a number of data store requests into the unit, a number of data fetch misses from the memory, a number of data fetch misses from the unit, a number of data retrieval hits from the memory, a number of data retrieval hits from the unit and combinations thereof.

4. The method of claim 1 , wherein said running the data processing system in the second mode comprises running the data processing system in a high power-saving mode by disabling the prefetch system from retrieving any lines of data from one of the memory and the 1:n level caches and from storing any lines of data in the first level cache, disabling the prefetch system from retrieving any lines of data from the memory and from storing any lines of data in the n level cache, and disabling store prefetching via stream filtering thereby reducing power consumption by the data processing system.

5. A data processing system program product for executing instructions in a data processing system, the data processing system program product comprising a data processing system-readable storage medium having data processing system-readable program code embodied in the medium, the data processing system having a processor, a unit that includes a first level cache and additional n levels of cache, a prefetch system and a memory, n being an integer greater than or equal to 0, the unit being operable to store lines of data in the first level cache, the first level cache being operable to store an integer w lines of data, the memory being operable to store an integer z lines of data, the unit being operable to store lines of data in the additional n levels of cache, each of the additional 1:n levels of cache being operable to store integer x 1:n lines of data, respectively, w<x 1 < . . . <x n-1 <x n <z, the processor being operable to access a line of data in the first level cache within a time t f , the processor being operable to access a line of data in each of the additional 1:n levels of cache within time t 1:n , respectively, t 1 < . . . <t n-1 <t n , the processor being operable to access a line of data in the memory within a time t m , t f <t 1 < . . . <t n-1 <t n <t m , the prefetch system being operable to retrieve up to y n lines of data from the memory and to store the up to y n lines of data in the n level cache, the prefetch system being operable to retrieve up to y f lines of data from one of the memory and 1:n levels of cache and to store the up to y f lines of data in the first level cache, the data processing system-readable program code being operable to instruct the data processing system to perform a method comprising: running the data processing system in a first mode; determining whether a second mode is required; and running the data processing system in the second mode when the second mode is required, wherein in the first mode, the prefetch system is enabled to: retrieve y f lines of data from one of the memory and the 1:n level caches and to store the y f lines of data in the first level cache, retrieve y n lines of data from the memory and store the y n lines of in the n level cache, and enable store prefetching via stream filtering, wherein the second mode is at least one of a low-power mode or a medium-power mode, wherein in the low-power mode the prefetch system is enabled to: retrieve b lines of data from one of the memory and the 1:n level caches and store the b lines of data in the first level cache, wherein b<y f , retrieve a lines of data from the memory and store the a lines of data in the n level cache, wherein a<y n , and disable store prefetching via stream filtering thereby reducing power consumption by the data processing system, and wherein in the medium-power mode the prefetch system is enabled to: disable prefetching into the first level cache, retrieve the a lines of data from the memory and store the a lines of data in the n level cache, wherein a<y n , and disable store prefetching via stream filtering thereby reducing power consumption by the data processing system.

6. The data processing system program product for executing instructions in a data processing system of claim 5 , wherein said determining whether a second mode is required comprises monitoring a workload characteristic of the data processing system.

7. The data processing system program product for executing instructions in a data processing system of claim 6 , wherein said monitoring a workload characteristic of the data processing system comprises monitoring at least one of a number of data store requests into the memory, a number of data store requests into the unit, a number of data fetch misses from the memory, a number of data fetch misses from the unit, a number of data retrieval hits from the memory, a number of data retrieval hits from the unit and combinations thereof.

8. The data processing system program product for executing instructions in a data processing system of claim 5 , wherein said running the data processing system in the second mode comprises running the data proceeding system in a high power-saving mode by disabling the prefetch system from retrieving any lines of data from one of the memory and the 1:n level caches and from storing any lines of data in the first level cache, disabling the prefetch system from retrieving any lines of data from the memory and from storing any lines of data in the n level cache, and disabling store prefetching via stream filtering thereby reducing power consumption by the data processing system.

9. A data processing system comprising: a processor; a unit; a first level cache within said unit; a prefetch system; n additional levels of cache; and a memory, wherein n is an integer greater than or equal to 0, wherein said unit is operable to store lines of data in the first level cache, wherein said first level cache is operable to store an integer w lines of data, wherein each of said additional 1:n levels of cache is operable to store integer x 0:n lines of data, respectively, wherein said memory is operable to store an integer z lines of data, wherein w<x 1 < . . . <x n-1 <x n <z, wherein said processor is operable to access a line of data in said first level cache within a time t f , to access a line of data in each of said additional 1:n levels of cache within time t 1:n , respectively, wherein t 1 < . . . <t n-1 <t n , wherein said processor is further operable to access a line of data in said memory within a time t m , wherein t f <t 1 < . . . <t n-1 <t n <t m , wherein said prefetch system is operable to retrieve up to y n lines of data from said memory and to store the up to y n lines of data in said n level cache, wherein said prefetch system is further operable to retrieve up to y f lines of data from one of said memory and said 1:n levels of cache and to store the up to y f lines of data in said first level cache, wherein said prefetch system is further operable to run in a first mode, wherein said processor is further operable to determine whether a second mode is required, wherein said prefetch system is further operable to run in the second mode when the second mode is required, wherein in the first mode, said prefetch system is enabled to: retrieve y f lines of data from one of the memory and the 1:n level caches and to store the y f lines of data in the first level cache, retrieve y n lines of data from the memory and store the y n lines of data in the n level cache, and enable store prefetching via stream filtering, wherein said second mode is at least one of a low-power mode or a medium-power mode, wherein in the low-power mode said prefetch system is enabled to: retrieve b lines of data from one of the memory and the 1:n level caches and store the b lines of data in the first level cache, wherein b<y f , retrieve a lines of data from the memory and store the a lines of data in the n level cache, wherein a<y n , and disable store prefetching via stream filtering thereby reducing power consumption by the data processing system, and wherein in the medium-power mode said prefetch system is enabled to: disable prefetching into the first level cache, retrieve the a lines of data from the memory and store the a lines of data in the n level cache, wherein a<y n , and disable store prefetching via stream filtering thereby reducing power consumption by the data processing system.

10. The data processing system of claim 9 , wherein said processor is operable to determine whether a second mode is required by monitoring a workload characteristic of at least one of said processor, said unit, said first level cache, said prefetch system, said n additional levels of cache and said memory.

11. The data processing system of claim 10 , wherein a workload characteristic of at least one of said processor, said unit, said first level cache, said prefetch system, said n additional levels of cache and said memory comprises at least one of a number of data store requests into said memory, a number of data store requests into said unit, a number of data fetch misses from said memory, a number of data fetch misses from said unit, a number of data retrieval hits from said memory, a number of data retrieval hits from said unit and combinations thereof.

12. The data processing system of claim 9 , wherein said running the prefetch system in the second mode comprises running the prefetch system in a high power-saving mode by disabling the prefetch system from retrieving any lines of data from one of the memory and the 1:n level caches and from storing any lines of data in the first level cache, disabling the prefetch system from retrieving any lines of data from the memory and from storing any lines of data in the n level cache, and disabling store prefetching via stream filtering thereby reducing power consumption by the data processing system.

13. A processor for use with a unit, a first level cache within the unit, n additional levels of cache and a memory, n being an integer greater than or equal to 0, the unit being operable to store lines of data in the first level cache, the first level cache being operable to store an integer w lines of data, each of the additional 1:n levels of cache being operable to store integer x 0:n lines of data, respectively, the memory being operable to store an integer z lines of data and w<x 1 < . . . <x n-1 <x n <z, said processor comprising: a processor portion; and a prefetch portion; wherein said processor portion is operable to access a line of data in the first level cache within a time t f , to access a line of data in each of the additional 1:n levels of cache within time t 1:n , respectively, wherein t 1 < . . . t n-1 <t n , wherein said processor portion is further operable to access a line of data in the memory within a time t m , wherein t f <t 1 < . . . <t n-1 <t n <t m , wherein said prefetch portion is operable to retrieve up to y n lines of data from the memory and to store the up to y n lines of data in the n level cache, wherein said prefetch portion is further operable to retrieve up to y f lines of data from one of the memory and the 1:n levels of cache and to store the up to y f lines of data in the first level cache, wherein said prefetch portion is further operable to run in a first mode, wherein said processor portion is further operable to determine whether a second mode is required, wherein said prefetch portion is further operable to run in the second mode when the second mode is required, wherein in the first mode, said prefetch portion is enabled to: retrieve y f lines of data from one of the memory and the 1:n level caches and to store the y f lines of data in the first level cache, retrieve y n lines of data from the memory and store the y n lines of data in the n level cache, and enable store prefetching via stream filtering, wherein the second mode is at least one of a low-power mode or a medium-power mode, wherein in the low-power mode said prefetch portion is enabled to: retrieve b lines of data from one of the memory and the 1:n level caches and store the b lines of data in the first level cache, wherein b<y f , retrieve a lines of data from the memory and store the a lines of data in the n level cache, wherein a<y n , and disable store prefetching via stream filtering thereby reducing power consumption by the data processing system, and wherein in the medium-power mode said prefetch portion is enabled to: disable prefetching into the first level cache, retrieve the a lines of data from the memory and store the a lines of data in the n level cache, wherein a<y n , and disable store prefetching via stream-filtering thereby reducing power consumption by the data processing system.

14. The processor of claim 13 , wherein said processor portion is operable to determine whether the second mode is required by monitoring a workload characteristic of said processor portion, said unit, said first level cache, said prefetch portion, said n additional levels of cache and said memory.

15. The processor of claim 14 , wherein a workload characteristic of at least one of said processor portion, said unit, said first level cache, said prefetch portion, said n additional levels of cache and said memory comprises at least one of a number of data store requests into said memory, a number of data store requests into said unit, a number of data fetch misses from said memory, a number of data fetch misses from said unit, a number of data retrieval hits from said memory, a number of data retrieval hits from said unit and combinations thereof.

16. The processor of claim 13 , wherein said running the prefetch portion in the second mode comprises running the prefetch portion in a high power-saving mode by disabling the prefetch portion from retrieving any lines of data from one of the memory and the 1:n level caches and from storing any lines of data in the first level cache, disabling the prefetch system from retrieving any lines of data from the memory and from storing any lines of data in the n level cache, and disabling store prefetching via stream filtering thereby reducing power consumption by the data processing system.