A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of enabling a memory controller associated with a remapping table to enable access to content in a memory system that includes asymmetric memory, the method comprising: receiving, at the memory controller, a request for an Input/Output (I/O) write to a first memory management unit-specified physical address; accessing a remapping table associated with a memory controller; using the remapping table to identify a first memory controller-specified physical address associated with the first memory management unit-specified physical address, the first memory controller-specified physical address corresponding to a first location within asymmetric memory storage; identifying a first disruption region within the asymmetric memory storage that includes the first location; writing contents from the first disruption region to a second disruption region; configuring the memory controller to process, between a time when the contents from the first disruption region begin to be written to the second disruption region and before a time when writing of the contents to be written to the second disruption region has been completed, read instructions from the memory management unit for requested content associated with a second memory management unit-specified physical address that is associated with the disruption region for the first memory-management unit specified physical address by reading the requested content from the first disruption region; and configuring the remapping table to associate the first memory management unit-specified physical address with a second memory controller-specified physical address corresponding to the second disruption region after determining that the contents have been written to the second disruption region, wherein the first disruption region and the second disruption region include physical addresses that are associated with characteristics that include corrupted content or nondeterministic read latency as a result of attempting to read data from the physical addresses concurrent with an I/O write being performed involving the physical addresses.
2. The method of claim 1 further comprising processing the request for the I/O write by writing data associated with the request for the I/O write to the second disruption region.
3. The method of claim 1 further comprising configuring the memory controller to process write instructions, from the memory management unit, to write to the second disruption region until a prior write operation has been completed.
4. The method of claim 1 further comprising leveraging the memory controller to align the first disruption region and the second disruption region including: after the data in the first disruption region has been written to the second disruption region, using the memory controller to write at least data newly-written to the second disruption region and distinct of data within the first disruption region to the first disruption region, and using the memory controller to process read instructions, as the data from the second disruption region is being written to the first disruption region, from the memory management unit for data residing in the first disruption region by reading from the second disruption region until the contents have been written to the first disruption region.
5. The method of claim 1 further comprising leveraging the memory controller to align the first disruption region and the second disruption region so that transferring the data between the first disruption region and the second disruption region only reflects the content that has been updated.
6. The method of claim 1 further comprising: receiving, at the memory controller from the memory management unit, a write instruction related to data that resides in the first disruption region; queuing the write instruction until the contents have been written to the second disruption region; and executing the write instruction in response to determining that the contents have been written to the second disruption region.
7. The method of claim 1 , further comprising: identifying, in the memory controller, two memory controller-specified physical addresses for the memory management unit-specified physical address as the data in the first disruption region is being written to the second disruption region; using a first memory controller-specified physical address associated with the first disruption region to process read instructions for data associated with the memory management unit-specified physical address; and using the second memory controller-specified physical address associated with the second disruption region to process write instructions for data associated with the memory management unit-specified physical address.
8. The method of claim 7 further comprising: detecting that the write instruction to the second memory controller-specified physical address is associated with a disruption region; and queuing the write instruction to the second memory controller-specified physical address until the second memory controller-specified physical address no longer represents a disruption region.
9. The method of claim 1 further comprising: exchanging, using the memory controller, asymmetric memory physical address information for the memory system across an interconnection; and automatically loading the requested data, using the asymmetric memory physical address information across the interconnection, in response to receiving a read instruction from the memory management unit.
10. The method of claim 1 wherein receiving, at the memory controller, the request for the Input/Output (I/O) write from the memory management unit-specified physical address includes: receiving the request for the I/O write on a Dual Inline Memory Module (DIMM); and routing the request for the I/O block write to a memory controller embedded within the DIMM.
11. The method of claim 1 wherein identifying the first disruption region includes identifying multiple areas of organized memory across multiple areas on a single device.
12. The method of claim 1 wherein identifying the first disruption region includes identifying multiple areas on multiple devices that are organized around a memory controller-specified physical address in the remapping table.
13. The method of claim 1 wherein accessing a remapping table associated with a memory controller includes: accessing a read translation table that is physically coupled to the asymmetric memory to exchange the first memory controller-specified physical address, and accessing a write translation table that is physically coupled to the asymmetric memory to exchange the first memory controller-specified physical address.
14. The method of claim 1 wherein accessing a remapping table associated with the memory controller includes: accessing a read translation table that is physically coupled to the asymmetric memory to exchange the first memory controller-specified physical address, and accessing a write translation table that is stored in a different location than the read location table, where the read translation table is physically coupled to the asymmetric memory to exchange the first memory controller-specified physical address.
15. The method of claim 14 wherein accessing the remapping table associated with the memory controller includes: accessing a read translation portion of the remapping table that is implemented as part of the memory controller logic to perform read operations, and accessing a write translation portion of the remapping table that is implemented as a software-managed table in order to perform write operations.
16. The method of claim 15 wherein accessing the write translation portion of the remapping table that is implemented as the software-managed table in order to perform write operations includes accessing the write translation portion of the remapping table that is implemented in association with an application, a hypervisor, an operating system, a CPU, or a memory controller.
17. The method of claim 1 wherein accessing a remapping table associated with a memory controller includes accessing the remapping table that is embedded as a DIMM-based memory controller.
18. The method of claim 1 wherein accessing a remapping table associated with a memory controller includes accessing several divided tables, where each of the divided tables are associated with two or more disruption regions within a DIMM.
19. The method of claim 1 wherein receiving, at the memory controller, the request for the Input/Output (I/O) write to the first memory management unit-specified physical address includes receiving, at the memory controller and from the memory management unit within the central processing unit (CPU), the request for an Input/Output (I/O) write to the first memory management unit-specified physical address.
20. The method of claim 1 wherein receiving, at the memory controller, the request for the Input/Output (I/O) write to the first memory management unit-specified physical address includes receiving, at the memory controller and from a system different than the memory management unit within the central processing unit (CPU), the request for an Input/Output (I/O) write to the first memory management unit-specified physical address.
21. The method of claim 1 further comprising configuring the memory controller to interface with symmetric memory and the asymmetric memory.
22. The method of claim 1 further comprising configuring the memory controller to interface with only the asymmetric memory.
23. The method of claim 1 further comprising configuring the memory controller to operate in a distributed mode, wherein the memory controller is configured to: perform read translations using memory controller logic, and perform write operations using a portion of the remapping table implemented as a software-managed table residing with an application, a hypervisor, an operating system, a CPU, or a memory controller.
24. The method of claim 1 wherein the asymmetric memory includes NOR flash memory and wherein using the remapping table to identify the first memory controller-specified physical address associated with the first memory management unit-specified physical address, the first memory controller-specified physical address corresponding to the first location within the asymmetric memory storage includes using the remapping table to identify the first memory controller-specified physical address associated with the first memory management unit-specified physical address, the first memory controller-specified physical address corresponding to the first location within the NOR flash memory.
25. The method of claim 1 wherein the asymmetric memory includes phase change memory and wherein using the remapping table to identify the first memory controller-specified physical address associated with the first memory management unit-specified physical address, the first memory controller-specified physical address corresponding to the first location within the asymmetric memory storage includes using the remapping table to identify the first memory controller-specified physical address associated with the first memory management unit-specified physical address, the first memory controller-specified physical address corresponding to the first location within the phase change memory.
26. This method of claim 1 wherein: the first disruption region includes a first bank within NOR flash memory and the second disruption region includes a second bank within the NOR flash memory, and wherein identifying a first disruption region includes identifying the first bank within the NOR flash memory.
27. A system that enables a memory controller associated with a remapping table to enable access to content in a memory system that includes asymmetric memory, the system comprising: means for receiving, at the memory controller, a request for an Input/Output (I/O) write to a first memory management unit-specified physical address; means for accessing a remapping table associated with a memory controller; means for using the remapping table to identify a first memory controller-specified physical address associated with the first memory management unit-specified physical address, the first memory controller-specified physical address corresponding to a first location within asymmetric memory storage; means for identifying a first disruption region within the asymmetric memory storage that includes the first location; means for writing contents from the first disruption region to a second disruption region; means for configuring the memory controller to process, between a time when the contents from the first disruption region begin to be written to the second disruption region and before a time when writing of the contents to be written to the second disruption region has been completed, read instructions from the memory management unit for requested content associated with a second memory management unit-specified physical address that is associated with the disruption region for the first memory-management unit specified physical address by reading the requested content from the first disruption region; and means for configuring the remapping table to associate the first memory management unit-specified physical address with a second memory controller-specified physical address corresponding to the second disruption region after determining that the contents have been written to the second disruption region, wherein the first disruption region and the second disruption region include physical addresses that are associated with characteristics that include corrupted content or nondeterministic read latency as a result of attempting to read data from the physical addresses concurrent with an I/O write being performed involving the physical addresses.
28. A system that enables a memory controller associated with a remapping table to enable access to content in a memory system that includes asymmetric memory, the system comprising: a processor; and a memory controller that is configured to: receive, at the memory controller, a request for an Input/Output (I/O) write to a first memory management unit-specified physical address; access a remapping table associated with a memory controller; use the remapping table to identify a first memory controller-specified physical address associated with the first memory management unit-specified physical address, the first memory controller-specified physical address corresponding to a first location within asymmetric memory storage; identify a first disruption region within the asymmetric memory storage that includes the first location; write contents from the first disruption region to a second disruption region; configure the memory controller to process, between a time when the contents from the first disruption region begin to be written to the second disruption region and before a time when writing of the contents to be written to the second disruption region has been completed, read instructions from the memory management unit for requested content associated with a second memory management unit-specified physical address that is associated with the disruption region for the first memory-management unit specified physical address by reading the requested content from the first disruption region; and configure the remapping table to associate the first memory management unit-specified physical address with a second memory controller-specified physical address corresponding to the second disruption region after determining that the contents have been written to the second disruption region, wherein the first disruption region and the second disruption region include physical addresses that are associated with characteristics that include corrupted content or nondeterministic read latency as a result of attempting to read data from the physical addresses concurrent with an I/O write being performed involving the physical addresses.
29. A computer program product on a non-transitory computer readable medium, the computer program product enabling a memory controller associated with a remapping table to enable access to content in a memory system that includes asymmetric memory and comprising instructions that when executed on a processor cause the processor to perform operations that include: receiving, at the memory controller, a request for an Input/Output (I/O) write to a first memory management unit-specified physical address; accessing a remapping table associated with a memory controller; using the remapping table to identify a first memory controller-specified physical address associated with the first memory management unit-specified physical address, the first memory controller-specified physical address corresponding to a first location within asymmetric memory storage; identifying a first disruption region within the asymmetric memory storage that includes the first location; writing contents from the first disruption region to a second disruption region; configuring the memory controller to process, between a time when the contents from the first disruption region begin to be written to the second disruption region and before a time when writing of the contents to be written to the second disruption region has been completed, read instructions from the memory management unit for requested content associated with a second memory management unit-specified physical address that is associated with the disruption region for the first memory-management unit specified physical address by reading the requested content from the first disruption region; and configuring the remapping table to associate the first memory management unit-specified physical address with a second memory controller-specified physical address corresponding to the second disruption region after determining that the contents have been written to the second disruption region, wherein the first disruption region and the second disruption region include physical addresses that are associated with characteristics that include corrupted content or nondeterministic read latency as a result of attempting to read data from the physical addresses concurrent with an I/O write being performed involving the physical addresses.
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October 20, 2008
April 10, 2012
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