A logic simulation apparatus includes: a jitter detector generation section 21 that generates information concerning a jitter circuit for determining whether a time variation occurs in signal passing between a first circuit and a second circuit, the first circuit configured to output a signal with a clock output from a predetermined clock source and the second circuit configured to output a signal with a clock output from a clock source different from the above predetermined clock source; and a constraint solver generation section 22 that generates information concerning a solver that is configured to create a signal to be output at an observation point using a logical expression of an output signal of the second circuit and output, based on the logical expression and output signal of the jitter detector circuit, a signal constrained by the output signal of the jitter detector circuit and output signal of the second circuit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A computer-readable recording medium storing a logic simulation program, the program allowing a computer to execute: a step that acquires information concerning a predetermined observation point on a simulation target; a step that generates information concerning a jitter detection circuit for determining whether a time variation occurs in a signal passing between a first circuit and a second circuit, the first circuit being arranged at the front stage on the simulation target relative to the predetermined observation point and configured to output a signal with a clock output from a predetermined clock source and the second circuit being arranged at the front stage on the simulation target relative to the predetermined observation point and at the rear stage relative to the first circuit and configured to output a signal with a clock output from a clock source different from the above predetermined clock source; and a step that generates information concerning a constraint circuit that is configured to create a signal to be output at the predetermined observation point using a logical expression of an output signal of the second circuit and output, based on the logical expression and output signal of the jitter detector circuit, a constraint signal constrained by the output signal of the jitter detector circuit and the output signal of the second circuit.
2. The computer-readable recording medium storing a logic simulation program according to claim 1 , wherein the step that generates information concerning the jitter detection circuit and step that generates information concerning the constraint circuit in the logic simulation program further generate information concerning the jitter detector circuit and constraint circuit in a range within which a time variation occurs in signal passing.
3. The computer-readable recording medium storing a logic simulation program according to claim 1 , wherein in the case where the number of the first circuits is plural and the number of the second circuits is singular, the step that generates information concerning the jitter detection circuit in the logic simulation program further generates, at one stage after each of jitter detector circuits generated based on the first circuits, information concerning a multiplexer circuit that outputs, to the second circuit, a signal based on the output signals from the jitter detector circuits and output signals from the first circuits.
5. A computer system constituting a logic simulation apparatus to execute a logic simulation program, comprising: an observation point acquisition section that acquires information concerning a predetermined observation point on a simulation target; a jitter detection circuit generation section that generates information concerning a jitter detection circuit for determining whether a time variation occurs in a signal passing between a first circuit and a second circuit, the first circuit being arranged at the front stage on the simulation target relative to the predetermined observation point and configured to output a signal with a clock output from a predetermined clock source and the second circuit being arranged at the front stage on the simulation target relative to the predetermined observation point and at the rear stage relative to the first circuit and configured to output a signal with a clock output from a clock source different from the above predetermined clock source; and a constraint circuit generation section that generates information concerning a constraint circuit that is configured to create a signal to be output at the predetermined observation point using a logical expression of an output signal of the second circuit and output, based on the logical expression and output signal of the jitter detector circuit, a constraint signal constrained by the output signal of the jitter detector circuit and the output signal of the second circuit.
6. The logic simulation apparatus according to claim 5 , wherein the jitter detection circuit generation section and constraint circuit generation section generate information concerning the jitter detector circuit and constraint circuit in a range within which a time variation occurs in signal passing.
7. The logic simulation apparatus according to claim 5 , wherein in the case where the number of the first circuits is plural and the number of the second circuits is singular, the jitter detection circuit generation section generates, at one stage after each of jitter detector circuits generated based on the first circuits, information concerning a multiplexer circuit that outputs, to the second circuit, a signal based on the output signals from the jitter detector circuits and output signals from the first circuits.
9. A logic simulation method in which a computer executes: a step that acquires information concerning a predetermined observation point on a simulation target; a step that generates information concerning a jitter detection circuit for determining whether a time variation occurs in a signal passing between a first circuit and a second circuit, the first circuit being arranged at the front stage on the simulation target relative to the predetermined observation point and configured to output a signal with a clock output from a predetermined clock source and the second circuit being arranged at the front stage on the simulation target relative to the predetermined observation point and at the rear stage relative to the first circuit and configured to output a signal with a clock output from a clock source different from the above predetermined clock source; and a step that generates information concerning a constraint circuit that is configured to create a signal to be output at the predetermined observation point using a logical expression of an output signal of the second circuit and output, based on the logical expression and output signal of the jitter detector circuit, a constraint signal constrained by the output signal of the jitter detector circuit and the output signal of the second circuit.
10. The logic simulation method according to claim 9 , wherein the step that generates information concerning the jitter detection circuit and step that generates information concerning the constraint circuit further generate information concerning the jitter detector circuit and constraint circuit in a range within which a time variation occurs in signal passing.
11. The logic simulation method according to claim 9 , wherein in the case where the number of the first circuits is plural and the number of the second circuits is singular, the step that generates information concerning the jitter detection circuit further generates, at one stage after each of jitter detector circuits generated based on the first circuits, information concerning a multiplexer circuit that outputs, to the second circuit, a signal based on the output signals from the jitter detector circuits and output signals from the first circuits.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 8, 2009
April 17, 2012
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.