A dual port SRAM cell includes an auxiliary driver transistor on each data node. The SRAM cell is capable of single sided write to each data node. The auxiliary driver transistors in addressed cells may be biased independently of half-addressed cells. During write and read operations, the auxiliary driver transistors may be floated or biased. Auxiliary driver transistors in half-addressed SRAM cells may be biased. During standby modes, the auxiliary driver transistors may be floated. During sleep modes, the auxiliary driver transistors may be biased at reduced voltages. The auxiliary driver transistors in each cell may be independent or may have a common source node within each cell. Additional single sided write ports and read buffers may be added. A process of operating an integrated circuit that includes performing a single-sided write bit-side low, a single-sided write bit-side high, and a read bit-side operation.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit, comprising: an array of SRAM cells, said SRAM cells being arranged in rows and columns, each said SRAM cell further including: a bit-side driver transistor, said bit-side driver transistor further including a gate node, a source node and a drain node; a bit-side data node, wherein said bit-side data node is connected to said drain node of said bit-side driver transistor; a bit-side load transistor, said bit-side load transistor further including a gate node, a source node and a drain node, wherein said drain node of said bit-side load transistor is connected to said bit-side data node; a bit-bar-side driver transistor, said bit-bar-side driver transistor further including a gate node, a source node and a drain node, wherein said gate node of said bit-bar-side driver transistor is connected to said bit-side data node; a bit-bar-side data node, wherein said bit-bar-side data node is connected to said drain node of said bit-bar-side driver transistor, to said gate node of said bit-side driver transistor and to said gate node of said bit-side load transistor; a bit-bar-side load transistor, said bit-bar-side load transistor further including a gate node, a source node and a drain node, wherein said drain node of said bit-bar-side load transistor is connected to said bit-bar-side data node, and said gate node of said bit-bar-side load transistor is connected to said bit-side data node; a bit-side auxiliary driver transistor, said bit-side auxiliary driver transistor further including a gate node, a source node and a drain node, wherein said drain node of said bit-side auxiliary driver transistor is connected to said bit-side data node, and said gate node of said bit-side auxiliary driver transistor is connected to said bit-bar-side data node; a bit-bar-side auxiliary driver transistor, said bit-bar-side auxiliary driver transistor further including a gate node, a source node and a drain node, wherein said drain node of said bit-bar-side auxiliary driver transistor is connected to said bit-bar-side data node, and said gate node of said bit-bar-side auxiliary driver transistor is connected to said bit-side data node; a bit-side passgate transistor, said bit-side passgate transistor further including a gate node, a first source/drain node and a second source/drain node, wherein said first source/drain node of said bit-side passgate transistor is connected to said bit-side data node, said second source/drain node of said bit-side passgate transistor is connected to a bit line, and said gate node of said bit-side passgate transistor is connected to a first word line; and a bit-bar-side passgate transistor, said bit-bar-side passgate transistor further including a gate node, a first source/drain node and a second source/drain node, wherein said first source/drain node of said bit-bar-side passgate transistor is connected to said bit-bar-side data node, said second source/drain node of said bit-bar-side passgate transistor is connected to a bit-bar line, and said gate node of said bit-bar-side passgate transistor is connected to a second word line; and an auxiliary driver transistor bias circuit coupled to said array of SRAM cells, said auxiliary driver transistor bias circuit being configured to provide bias voltages to said source node of said bit-side auxiliary driver transistor and said source node of said bit-bar-side auxiliary driver transistor.
2. The integrated circuit of claim 1 , in which said auxiliary driver transistor bias circuit is configured to provide a first set of bias voltages to said source node of said bit-side auxiliary driver transistor and said source node of said bit-bar-side auxiliary driver transistor in a half-addressed SRAM cell and independently provide a second set of bias voltages to said source node of said bit-side auxiliary driver transistor and said source node of said bit-bar-side auxiliary driver transistor in an addressed SRAM cell.
3. The integrated circuit of claim 1 , in which each said SRAM cell further includes a second bit-side passgate transistor, said second bit-side passgate transistor further including a gate node, a first source/drain node and a second source/drain node, wherein said first source/drain node of said second bit-side passgate transistor is connected to said bit-side data node, said second source/drain node of said second bit-side passgate transistor is connected to a second bit line, and said gate node of said second bit-side passgate transistor is connected to a third word line, such that a single sided write bit-side operation may be performed with said second bit line through said second bit-side passgate transistor.
4. The integrated circuit of claim 3 , in which each said SRAM cell further includes a second bit-bar-side passgate transistor, said second bit-bar-side passgate transistor further including a gate node, a first source/drain node and a second source/drain node, wherein said first source/drain node of said second bit-bar-side passgate transistor is connected to said bit-bar-side data node, said second source/drain node of said second bit-bar-side passgate transistor is connected to a second bit-bar line, and said gate node of said second bit-bar-side passgate transistor is connected to a fourth word line, such that a single sided write bit-bar-side operation may be performed with said second bit-bar line through said second bit-bar-side passgate transistor.
5. The integrated circuit of claim 1 , in which each said SRAM cell further includes a bit-side read buffer coupled to said bit-bar-side data node, said bit-side read buffer further including a bit-side access transistor and a bit-side read buffer driver transistor, wherein: said bit-side access transistor includes a gate node, a first source/drain node and a second source/drain node, wherein said first source/drain node of said bit-side access transistor is connected to a second bit line and said gate node of said bit-side access transistor is connected to a third word line; and said bit-side read buffer driver transistor includes a gate node and a source/drain node, wherein said gate node of said bit-side read buffer driver transistor is connected to said bit-bar-side data node and said source/drain node of said bit-side read buffer driver transistor is connected to said second source/drain node of said bit-side access transistor; such that a read operation may be performed from said bit-bar-side data node through said bit-side read buffer to said second bit line.
6. The integrated circuit of claim 5 , in which each said SRAM cell further includes a bit-bar-side read buffer coupled to said bit-side data node, said bit-bar-side read buffer further including a bit-bar-side access transistor and a bit-bar-side read buffer driver transistor, wherein: said bit-bar-side access transistor includes a gate node, a first source/drain node and a second source/drain node, wherein said first source/drain node of said bit-bar-side access transistor is connected to a second bit-bar line and said gate node of said bit-bar-side access transistor is connected to a fourth word line; and said bit-bar-side read buffer driver transistor includes a gate node and a source/drain node, wherein said gate node of said bit-bar-side read buffer driver transistor is connected to said bit-side data node and said source/drain node of said bit-bar-side read buffer driver transistor is connected to said second source/drain node of said bit-bar-side access transistor; such that a read operation may be performed from said bit-bar-side data node through said bit-bar-side read buffer to said second bit-bar line.
7. The integrated circuit of claim 1 , in which: said bit-side driver transistor is an NMOS transistor; said bit-side load transistor is a PMOS transistor; said bit-bar-side driver transistor is an NMOS transistor; said bit-bar-side load transistor is a PMOS transistor; said bit-side auxiliary driver transistor is an NMOS transistor; and said bit-bar-side auxiliary driver transistor is an NMOS transistor.
8. The integrated circuit of claim 1 , in which: said bit-side driver transistor is a PMOS transistor; said bit-side load transistor is an NMOS transistor; said bit-bar-side driver transistor is a PMOS transistor; said bit-bar-side load transistor is an NMOS transistor; said bit-side auxiliary driver transistor is a PMOS transistor; and said bit-bar-side auxiliary driver transistor is a PMOS transistor.
9. An integrated circuit, comprising: an array of SRAM cells, said SRAM cells being arranged in rows and columns, each said SRAM cell further including: a bit-side driver transistor, said bit-side driver transistor further including a gate node, a source node and a drain node; a bit-side data node, wherein said bit-side data node is connected to said drain node of said bit-side driver transistor; a bit-side load transistor, said bit-side load transistor further including a gate node, a source node and a drain node, wherein said drain node of said bit-side load transistor is connected to said bit-side data node; a bit-bar-side driver transistor, said bit-bar-side driver transistor further including a gate node, a source node and a drain node, wherein said gate node of said bit-bar-side driver transistor is connected to said bit-side data node; a bit-bar-side data node, wherein said bit-bar-side data node is connected to said drain node of said bit-bar-side driver transistor, to said gate node of said bit-side driver transistor and to said gate node of said bit-side load transistor; a bit-bar-side load transistor, said bit-bar-side load transistor further including a gate node, a source node and a drain node, wherein said drain node of said bit-bar-side load transistor is connected to said bit-bar-side data node, and said gate node of said bit-bar-side load transistor is connected to said bit-side data node; a bit-side auxiliary driver transistor, said bit-side auxiliary driver transistor further including a gate node, a source node and a drain node, wherein said drain node of said bit-side auxiliary driver transistor is connected to said bit-side data node, and said gate node of said bit-side auxiliary driver transistor is connected to said bit-bar-side data node; a bit-bar-side auxiliary driver transistor, said bit-bar-side auxiliary driver transistor further including a gate node, a source node and a drain node, wherein said drain node of said bit-bar-side auxiliary driver transistor is connected to said bit-bar-side data node, said gate node of said bit-bar-side auxiliary driver transistor is connected to said bit-side data node, and said source node of said bit-bar-side auxiliary driver transistor is connected to said source node of said bit-side auxiliary driver transistor; a bit-side passgate transistor, said bit-side passgate transistor further including a gate node, a first source/drain node and a second source/drain node, wherein said first source/drain node of said bit-side passgate transistor is connected to said bit-side data node, said second source/drain node of said bit-side passgate transistor is connected to a bit line, and said gate node of said bit-side passgate transistor is connected to a first word line; and a bit-bar-side passgate transistor, said bit-bar-side passgate transistor further including a gate node, a first source/drain node and a second source/drain node, wherein said first source/drain node of said bit-bar-side passgate transistor is connected to said bit-bar-side data node, said second source/drain node of said bit-bar-side passgate transistor is connected to a bit-bar line, and said gate node of said bit-bar-side passgate transistor is connected to a second word line; and an auxiliary driver transistor bias circuit coupled to said array of SRAM cells, said auxiliary driver transistor bias circuit being configured to provide bias voltages to said source node of said bit-side auxiliary driver transistor and said source node of said bit-bar-side auxiliary driver transistor.
10. A process of operating an integrated circuit, comprising the steps of: performing a single sided write bit-side low operation on an addressed SRAM cell, by a process including the step of biasing a source nodes of a bit-side auxiliary driver transistor and a source node of a bit-bar-side auxiliary driver transistor in a half-addressed SRAM cell to a low voltage; performing a single sided write bit-side high operation on said addressed SRAM cell, by a process including the step of biasing said source node of said bit-side auxiliary driver transistor and said source node of said bit-bar-side auxiliary driver transistor in said half-addressed SRAM cell to a low voltage; and performing a read bit-side operation on said addressed SRAM cell, by a process including the steps of biasing said source node of said bit-side auxiliary driver transistor and said source node of said bit-bar-side auxiliary driver transistor in said half-addressed SRAM cell to a low voltage, and biasing a source node of a bit-side auxiliary driver transistor and a source node of a bit-bar-side auxiliary driver transistor in an addressed SRAM cell to a low voltage.
11. The process of claim 10 , further including the step of transitioning said addressed SRAM cell and said half-addressed SRAM cell to a standby mode, by a process including the steps of floating said source node of said bit-side auxiliary driver transistor in said addressed SRAM cell, floating said source node of said bit-bar-side auxiliary driver transistor in said addressed SRAM cell, floating said source node of said bit-side auxiliary driver transistor in said half-addressed SRAM cell, floating said source node of said bit-bar-side auxiliary driver transistor in said half-addressed SRAM cell.
12. The process of claim 10 , further including the step of transitioning said addressed SRAM cell and said half-addressed to a sleep mode, by a process including the steps of biasing said source node of said bit-side auxiliary driver transistor in said addressed SRAM cell to a voltage on said bit-side driver transistor in said addressed SRAM cell, biasing said source node of said bit-bar-side auxiliary driver transistor in said addressed SRAM cell to a voltage on said bit-bar-side driver transistor in said addressed SRAM cell, biasing said source node of said bit-side auxiliary driver transistor in said half-addressed SRAM cell to a voltage on said bit-side driver transistor in said half-addressed SRAM cell, biasing said source node of said bit-bar-side auxiliary driver transistor in said half-addressed SRAM cell to a voltage on said bit-bar-side driver transistor in said half-addressed SRAM cell.
13. The process of claim 10 , in which said step of performing said single sided write bit-side low operation includes the step of floating said source node of said bit-side auxiliary driver transistor in said addressed SRAM cell.
14. The process of claim 10 , in which said step of performing said single sided write bit-side low operation includes the step of floating said source node of said bit-bar-side auxiliary driver transistor in said addressed SRAM cell.
15. The process of claim 10 , in which said step of performing said single sided write bit-side high operation includes the step of floating said source node of said bit-side auxiliary driver transistor in said addressed SRAM cell.
16. The process of claim 10 , in which said step of performing said single sided write bit-side high operation includes the step of floating said source node of said bit-bar-side auxiliary driver transistor in said addressed SRAM cell.
17. The process of claim 10 , in which: said step of performing said single sided write bit-side low operation includes the step of biasing said source node of said bit-bar-side auxiliary driver transistor in said addressed SRAM cell to a high voltage; and said step of performing said single sided write bit-side high operation includes the step of biasing said source node of said bit-side auxiliary driver transistor in said addressed SRAM cell to a high voltage.
18. The process of claim 10 , in which said step of performing said single sided write bit-side low operation includes the step of determining if a low voltage was successfully transferred to a bit-side data node of said addressed SRAM cell.
19. The process of claim 10 , in which said step of performing said single sided write bit-side high operation includes the step of determining if a high voltage was successfully transferred to a bit-side data node of said addressed SRAM cell.
20. The process of claim 10 , in which said step of performing said read bit-side operation includes the step of determining if a voltage on a bit-side data node was successfully transferred to a bit data line of said addressed SRAM cell.
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May 19, 2010
April 24, 2012
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