An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A structure comprising: a first semiconductor structure including a first semiconductor substrate comprising at least one semiconductor device; an array of conductive pins located on said first semiconductor substrate; a second semiconductor structure including a second semiconductor substrate comprising at least another semiconductor device; an array of conductive pads located on said second semiconductor substrate; and at least one localized network of programmable contacts connected to a subset of said array of conductive pads, wherein said array of conductive pins abut said array of conductive pads, wherein at least one first programmable contact in said at least one localized network of programmable contacts is programmed, and wherein at least one second programmable contact in said at least one localized network of programmable contacts is unprogrammed.
2. The structure of claim 1 , wherein each conductive pad in said subset is connected to a programmable contact, and wherein all programmable contacts in said subset are connected to a signal port within said second semiconductor substrate by a parallel connection.
3. The structure of claim 1 , wherein said first semiconductor structure and said second semiconductor structure are separated from each other, and wherein all programmable contacts in said at least one localized network of programmable contacts are in an unprogrammed state.
4. The structure of claim 1 , wherein each conductive pad electrically connected to said at least one first programmable contact is resistively connected to a signal port, and wherein each conductive pad electrically connected to at least one second programmable contact is electrically disconnected from said signal port.
5. The structure of claim 4 , wherein each conductive pad resistively connected to said at least one first programmable contact underlies or overlies a conductive pin.
6. The structure of claim 1 , wherein said at least one localized network of programmable contacts include a plurality of localized networks of programmable contacts, and wherein at least one conductive pad in said array of conductive pads is resistively connected to a first-group programmable contact in a first localized network of programmable contacts and to a second-group programmable contact in a second localized network of programmable contacts.
7. The structure of claim 6 , wherein a plurality of conductive pads in said array of conductive pads is resistively connected to a first-group programmable contact in said first localized network of programmable contacts and to a second-group programmable contact in said second localized network of programmable contacts.
8. The structure of claim 1 , wherein programmable contacts in said at least one localized network of programmable contacts comprises at least one of an electrically programmable fuse (eFuse), an electrically programmable antifuse, a field programmable gate array (FPGA), programmable gate array (PGA), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically programmable read only memory (EEPROM), and any other programmable logic device (PLD).
9. The structure of claim 1 , wherein said array of conductive pins and said array of conductive pads comprise a metallic material.
10. A structure comprising: a first semiconductor structure including a first semiconductor substrate comprising at least one semiconductor device; an array of conductive pins located on said first semiconductor substrate; a second semiconductor structure including a second semiconductor substrate comprising at least another semiconductor device; an array of conductive pads located on said second semiconductor substrate; and at least one localized network of programmable contacts connected to a subset of said array of conductive pads, wherein said array of conductive pins abut said array of conductive pads, wherein said array of conductive pins has a first pitch in a direction, wherein said array of conductive pads has a second pitch in said direction, and wherein the first pitch is greater than the second pitch and a first spacing in the direction between a neighboring pair of conductive pins is greater than the second pitch.
11. The structure of claim 10 , wherein said first pitch is from about 0.2 micron to about 3 microns, and wherein conductive pins in said array of conductive pins has a diameter from about 0.1 micron to about 2 microns.
12. The structure of claim 10 , wherein each conductive pad in said subset is connected to a programmable contact, and wherein all programmable contacts in said subset are connected to a signal port within said second semiconductor substrate by a parallel connection.
13. The structure of claim 10 , wherein said first semiconductor structure and said second semiconductor structure are separated from each other, and wherein all programmable contacts in said at least one localized network of programmable contacts are unprogrammed.
14. The structure of claim 10 , wherein at least one first programmable contact in said at least one localized network of programmable contacts is programmed, and wherein at least one second programmable contact in said at least one localized network of programmable contacts is unprogrammed.
15. The structure of claim 10 , wherein each conductive pad electrically connected to said at least one first programmable contact is resistively connected to a signal port, and wherein each conductive pad electrically connected to at least one second programmable contact is electrically disconnected from said signal port.
16. The structure of claim 15 , wherein each conductive pad resistively connected to said at least one first programmable contact underlies or overlies a conductive pin.
17. The structure of claim 10 , wherein said at least one localized network of programmable contacts include a plurality of localized networks of programmable contacts, and wherein at least one conductive pad in said array of conductive pads is resistively connected to a first-group programmable contact in a first localized network of programmable contacts and to a second-group programmable contact in a second localized network of programmable contacts.
18. The structure of claim 10 , wherein programmable contacts in said at least one localized network of programmable contacts comprises at least one of an electrically programmable fuse (eFuse), an electrically programmable antifuse, a field programmable gate array (FPGA), programmable gate array (PGA), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically programmable read only memory (EEPROM), and any other programmable logic device (PLD).
19. The structure of claim 10 , wherein said array of conductive pins and said array of conductive pads comprise a metallic material.
20. A structure comprising: a first semiconductor structure including a first semiconductor substrate comprising at least one semiconductor device; an array of conductive pins located on said first semiconductor substrate and having a first pitch in a direction; a second semiconductor structure including a second semiconductor substrate comprising at least another semiconductor device; and an array of conductive pads located on said second semiconductor substrate and having a second pitch in said direction, wherein said first pitch is greater than said second pitch and a first spacing in said direction between a neighboring pair of conductive pins is greater than said second pitch.
21. The structure of claim 20 , wherein said array of conductive pins is a first rectangular array or a first hexagonal array having said first pitch in a first direction and a third pitch in a second direction, and wherein said array of conductive pads is a second rectangular array or a second hexagonal array having said second pitch in said first direction and a fourth pitch in said second direction, wherein said third pitch is greater than said fourth pitch, and wherein a second spacing in said second direction between a neighboring pair of conductive pins is greater than said fourth pitch.
22. The structure of claim 20 , further comprising at least one localized network of programmable contacts located in said second semiconductor substrate and resistively connected to a subset of said array of conductive pads, wherein each programmable contact in said at least one localized network is connected to a conductive pad in a series connection, and wherein all programmable contacts in said at least one localized network is connected is connected to a signal port in a parallel connection.
23. The structure of claim 20 , further comprising at least one localized network of programmable contacts located in said second semiconductor substrate, wherein said array of conductive pins abut said array of conductive pads, wherein at least one first programmable contact in said at least one localized network of programmable contacts is programmed, and wherein at least one second programmable contact in said at least one localized network of programmable contacts is unprogrammed.
24. The structure of claim 23 , wherein each conductive pad electrically connected to said at least one first programmable contact is resistively connected to a signal port, and wherein each conductive pad electrically connected to at least one second programmable contact is electrically disconnected from said signal port.
25. The structure of claim 23 , wherein each conductive pad resistively connected to said at least one first programmable contact underlies or overlies a conductive pin.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 27, 2009
May 8, 2012
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