In a data compensating circuit and a display apparatus having the same, a previous compressed data compressed from a previous frame data is previously stored in a memory, a decoder decompresses the previous compressed data from the memory to output a previous decompressed data, a coder-decoder compresses a present frame data into a present compressed data to store the present compressed data in the memory and decompresses the present compressed data to output a present decompressed data. A first processor outputs a difference value between the previous decompressed data and the present decompressed data, a second processor adds the present frame data and the difference value to generate a previous re-decompressed data. A compensator outputs a present compensation data based on the previous re-decompressed data and the present frame data. Thus, the size of the memory may be reduced while preventing damage of data.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data compensating circuit comprising: a memory storing previous compressed data, into which previous frame data is compressed; a decoder decompressing the previous compressed data that is read out from the memory to output previous decompressed data during a present frame; a coder-decoder compressing present frame data into present compressed data to store the present compressed data in the memory and decompressing the present compressed data to output present decompressed data during the present frame; a first processor outputting a first difference value indicating a difference between the previous decompressed data and the present decompressed data; a second processor outputting previous re-decompressed data based on the first difference value and the present frame data; and a compensator compensating the present frame data based on the previous re-decompressed data and the present frame data to output present compensation data.
2. The data compensating circuit of claim 1 , wherein the previous re-decompressed data is the sum of the present frame data and the first difference value.
3. The data compensating circuit of claim 2 , wherein the compensator outputs the present compensation data having the same value as the present frame data when a second difference value indicating a difference between the previous re-decompressed data and the present frame data is smaller than a predetermined first reference value, and outputs the present compensation data increased by a predetermined compensated value compared to the present frame data when the second difference value is larger than the first reference value.
4. The data compensating circuit of claim 3 , wherein the second processor outputs the previous re-decompressed data identical to the present frame data when the first difference value is equal to zero, and the present compensation data is identical to the present frame data.
5. The data compensating circuit of claim 1 , wherein the memory has a size that is smaller than 2 m (m represents a number of bits of the present frame data).
6. The data compensating circuit of claim 5 , wherein the memory has a size of 2 m/3 .
7. The data compensating circuit of claim 6 , wherein the decoder decompresses the previous compressed data of m/3 bits into the previous decompressed data of m bits, and the coder-decoder compresses the present frame data of m bits into the present compressed data of m/3 bits.
8. A data compensating circuit comprising: a first memory in which (n−2)th data compressed from (n−2)th frame data (n represents a present frame) is previously stored; a second memory in which (n−1)th data compressed from (n−1)th frame data is previously stored; a first decoder decompressing the (n−2)th compressed data to output an (n−2)th decompressed data during an n-th frame; a second decoder decompressing the (n−1)th compressed data to output (n−1)th decompressed data during the n-th frame; a coder-decoder compressing the n-th frame data into n-th compressed data to provide the n-th compressed data to the second memory during the n-th frame, and decompressing the n-th compressed data to output n-th decompressed data; a first processor outputting a first difference value indicating a difference between the (n−2)th decompressed data and the n-th decompressed data; a second processor outputting (n−2)th re-decompressed data based on the first difference value and the n-th frame data; a third processor outputting a second difference value indicating a difference between the (n−1)th decompressed data and the n-th decompressed data; a fourth processor outputting an (n−1)th re-decompressed data based on the second difference value and the n-th frame data; and a compensator compensating the (n−1)th re-decompressed data based on the (n−2)th re-decompressed data, the (n−1)th re-decompressed data and the n-th frame data to output (n−1)th compensation data.
9. The data compensating circuit of claim 8 , wherein the (n−2)th re-decompressed data is the sum of the n-th frame data and the first difference value, and the (n−1)th re-decompressed data is the sum of the n-th frame data and the second difference value.
10. The data compensating circuit of claim 8 , wherein each of the first and second memories is smaller than 2 m (m represents a number of bits of the n-th frame data).
11. The data compensating circuit of claim 10 , wherein each of the first and second memories has a size of 2 m/3 .
12. A data compensating circuit comprising: a first memory in which (n−2)th data compressed from (n−2)th frame data (n represents a present frame) is previously stored; a second memory in which (n−1)th data compressed from (n−1)th frame data is previously stored; a coder converting n-th frame data into n-th compressed data during an n-th frame; a comparator comparing the (n−2)th compressed data, the (n−1)th compressed data and the n-th compressed data with each other to output a selection signal; a decoder decompressing the n-th compressed data, the (n−1)th compressed data and the (n−2)th compressed data into n-th decompressed data, (n−1)th decompressed data and (n−2)th decompressed data, respectively; a compensator outputting first compensation data based on the n-th decompressed data, the (n−1)th decompressed data, and the (n−2)th decompressed data; and a data selector outputting either the n-th frame data or the first compensation data as output data thereof in response to the selection signal.
13. The data compensating circuit of claim 12 , wherein the compensator comprises: a first compensator outputting second compensation data based on the (n−1)th decompressed data and the (n−2)th decompressed data; and a second compensator outputting first compensation data based on the second compensation data and the n-th decompressed data.
14. The data compensating circuit of claim 13 , wherein the second compensator outputs an intermediate value between the second compensation data and the n-th decompressed data as the first compensation data.
15. The data compensating circuit of claim 13 , wherein the first compensator outputs the (n−1)th decompressed data when a difference value indicating a difference between the (n−2)th decompressed data and the (n−1)th decompressed data is smaller than a predetermined reference value, and outputs the second compensation data increased by a predetermined compensated value compared to the (n−1)th decompressed data when the difference value is larger than the predetermined reference value.
16. The data compensating circuit of claim 12 , wherein the comparator outputs the selection signal having a first state when the n-th compressed data is equal to the (n−2)th compressed data and the (n−1)th compressed data, and outputs the selection signal having a second state when the n-th compressed data is different from the (n−2)th compressed data and the (n−1)th compressed data.
17. The data compensating circuit of claim 16 , wherein the data selector outputs the n-th frame data as the output data in response to the selection signal having the first state, and outputs the first compensation data as the output data in response to the selection signal having the second state.
18. The data compensating circuit of claim 12 , wherein each of the first and second memories has a size that is smaller than 2 m (m represents a number of bits of the n-th frame data).
19. A display apparatus comprising: a data compensating circuit generating a present compensation data based on previous frame data and present frame data; a data driving circuit outputting a data voltage corresponding to the present compensation data in response to a data control signal; a gate driving circuit outputting a gate voltage in response to a gate control signal; and a display part displaying an image in response to the data voltage and the gate voltage, the data compensating circuit comprising: a memory in which previous compressed data compressed from the previous frame data is previously stored; a decoder decompressing the previous compressed data that is read out from the memory to output previous decompressed data during a present frame; a coder-decoder compressing the present frame data into present compressed data to store the present compressed data into the memory, and decompressing the present compressed data to output present decompressed data during a present frame; a first processor outputting a first difference value indicating a difference between the previous decompressed data and the present decompressed data; a second processor outputting a previous re-decompressed data based on the first difference value and the present frame data; and a compensator compensating the present frame data based on the previous re-decompressed data and the present frame data to output present compensation data.
20. The display apparatus of claim 19 , wherein the previous re-decompressed data is the sum of the present frame data and the first difference value.
21. The display apparatus of claim 19 , wherein the memory has a size that is smaller than 2 m (m represents a number of bits of the present frame data).
22. The display apparatus of claim 19 , further comprising a timing controller that applies the data control signal and the gate control signal to the data driving circuit and the gate driving circuit, respectively, in response to an external control signal.
23. The display apparatus of claim 22 , wherein the timing controller is formed in a chip-shape, and the data compensating circuit is built into the timing controller.
24. The display apparatus of claim 19 , wherein the display part comprises a plurality of pixels arranged in a matrix configuration thereon, each of the pixels comprises: a thin film transistor outputting the data voltage in response to the gate voltage; and a liquid crystal capacitor charging an electric potential difference between the data voltage and a predetermined reference voltage thereinto.
25. A display apparatus comprising: a data compensating circuit receiving n-th frame data to compensate the n-th frame data for generating compensated data as output data during the n-th frame; a data driving circuit converting the compensated data into a data voltage in response to a data control signal to output the data voltage; a gate driving circuit outputting a gate voltage in response to a gate control signal; and a display part displaying an image in response to the data voltage and the gate voltage, the data compensating circuit comprising: a first memory in which (n−2)th compressed data compressed from (n−2)th frame data is previously stored; a second memory in which (n−1)th compressed data compressed from (n−1)th frame data is previously stored; a coder converting the n-th frame data into n-th compressed data during an n-th frame; a comparator comparing the (n−2)th compressed data, the (n−1)th compressed data, and the n-th compressed data with each other to output a selection signal; a decoder decompressing the n-th compressed data, the (n−1)th compressed data and the (n−2)th compressed data into n-th decompressed data, (n−1)th decompressed data, and (n−2)th decompressed data, respectively; a compensator outputting first compensation data based on the n-th decompressed data, the (n−1)th decompressed data, and the (n−2)th decompressed data; and a data selector outputting either the n-th frame data or the first compensation data as the output data in response to the selection signal.
26. The display apparatus of claim 25 , wherein the compensator comprises: a first compensator outputting second compensation data based on the (n−1)th decompressed data and the (n−2)th decompressed data; and a second compensator outputting the first compensation data based on the second compensation data and the n-th decompressed data.
27. The display apparatus of claim 25 , wherein the comparator outputs the selection signal having a first state when the n-th compressed data is equal to the (n−2)th compressed data and the (n−1)th compressed data, and outputs the selection signal having a second state when the n-th compressed data is different from the (n−2)th compressed data and the (n−1)th compressed data.
28. The display apparatus of claim 27 , wherein the data selector outputs the n-th frame data as the output data in response to the selection signal having the first state, and outputs the first compensation data as the output data in response to the selection signal having the second state.
29. The display apparatus of claim 25 , further comprising a timing controller that applies the data control signal and the gate control signal to the data driving circuit and the gate driving circuit, respectively, in response to a control signal from an exterior.
30. The display apparatus of claim 29 , wherein the timing controller is formed in a chip-shape and the data compensating circuit is built into the timing controller.
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June 1, 2007
May 8, 2012
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