Process for running programs on processors and corresponding processor system

1. A process for executing programs on a multiprocessor system having a plurality of processors, having an instruction set architecture, each of the processors being able to execute, at each processing cycle, a respective maximum number of instructions, the process comprising: retrieving a first set of instructions as compiled instruction words having a first length and executable on a first processor of said plurality; and modifying, during runtime of one of the programs, at least some of the instruction words of the first set of instructions by converting them into modified-instruction words executable on a second processor of said plurality, said modification operation having at least one operation selected from the group of: splitting said instruction words into modified-instruction words and managing a context of execution of the modified-instruction words by the second processor; and entering in the modified-instruction words no-operation instructions.

2. The process according to claim 1 , further comprising: retrieving a second set of instructions as compiled instruction words having a second length and executable on the second processor; and modifying at least some of the instruction words of the second set of instructions into second modified-instruction words executable on said first processor of said plurality.

3. The process according to claim 2 wherein said first set of instructions and said second set of instructions have, respectively, a first and a second maximum length with said first maximum length greater than said second maximum length, a quotient between said first maximum length and said second maximum length having a given value with a possible presence of a remainder and in that the procedure comprises the operations of: selectively modifying instructions in the first set of instructions by: splitting said first instruction words into a number of said first modified-instruction words equal to the value of said quotient; and in the presence of said remainder, adding to said first modified-instruction words a further modified-instruction word of length equal to said second maximum length, said second maximum length being obtained by entering into said further first modified-instruction word a set of no-operation instructions; and selectively modifying instructions in the second set of instructions by: adding to said second instruction words of said second maximum length a number of no-operation instructions equal to a difference between said first maximum length and said second maximum length.

4. The process according to claim 1 , further comprising: encoding said instructions on a given number of bits, said number of bits having a first bit identifying a length of instruction word executable on a processor of said plurality; associating to said given number of bits a respective appendix having a set of further bits identifying lengths of instruction words executable on different processors of said plurality; identifying for each of said instructions a processor of said plurality designed to execute said instruction, said identified processor being able to process for each processing cycle a given length of instruction word; and entering in the position of said first identifier bit a chosen bit between said further bits of said appendix, said chosen bit identifying the length of instruction word that can be executed by said identified processor.

5. The process according to claim 4 , further comprising the operation of erasing said respective appendix before execution of the instruction.

6. The process according to claim 4 wherein said chosen bit is entered in the position of said first identifier bit in a step chosen from among: decoding of the instruction in view of the execution; re-filling of the cache associated to said identified processor; and decompression of the instruction in view of the execution.

7. The process according to claim 1 , further comprising: alternatively distributing the execution of instructions for programs between the processors of said plurality, said instructions being directly executable by the processors of said plurality in conditions of binary compatibility.

8. The process according to claim 1 , further comprising the operation of selectively distributing the execution of said instructions among the processors of said plurality, distributing dynamically the computational load of said processors.

9. The process according to claim 1 , further comprising the operation of selectively distributing the execution of said instructions between said processors of said plurality with the criterion of equalizing the operating frequency of the processors of said plurality.

10. The process according to claim 1 , further comprising the operation of performing a control process executed by at least one of the processors of said plurality so as to equalize its own workload with respect to the other processors of said multiprocessor system.

11. The process according to claim 1 , further comprising the operation of drawing up a table accessible by said control process, said table having items selected from the group of: a list of processes being executed or suspended on any processor of said plurality of processors; the progressive number thereof according to the order of activation; the percentage of maximum power of the processor that is used by said process; the execution time, said time, if zero, indicating that the process is temporarily suspended from being executed; the amount of memory of the system used by the process to be able to execute the function for which it is responsible; the maximum length of the long instruction that the VLIW processor can execute and for which it had been generated during compiling; maximum length of the long instruction of the VLIW processor on which it is executed; and the address of the portion of memory in which the data and the instructions are stored.

12. The process according to claim 1 , further comprising: executing, by the second processor, the modified instruction words.

13. A multiprocessor system comprising: a first processor having a given instruction set architecture and configured to execute programs with instruction words of a first length; a second processor having the given instruction set architecture and configured to execute programs with instruction words of a second length; and means for modifying, during runtime of a program having instructions words of the first length, at least some of the instruction words of the program by converting them into modified-instruction words executable on the second processor, said modifying including at least one operation selected from the group of: splitting said instruction words into modified-instruction words and managing a context of execution of the modified-instruction words by the second processor; and entering in the modified-instruction words no-operation instructions.

14. The multiprocessor system according to claim 13 wherein said processors are all of the Very Long Instruction Word (VLIW) type.

15. The multiprocessor system according to claim 13 comprising at least one VLIW processor and at least one superscalar processor.

16. The multiprocessor system of claim 13 , further comprising: means for selectively controlling execution of the modified instruction words by the second processor.

17. The multiprocessor system of claim 13 , further comprising means for converting instruction words of the second length compiled for execution on the second processor into modified instruction words of the first length executable on the first processor.

18. The multiprocessor system of claim 17 wherein the means for converting instruction words of the second length compiled for execution on the second processor is configured to selectively modify instructions of the second length by: adding to instruction words of said second length a number of no-operation instructions equal to a difference between said first length and said second length.

19. A process of directing instruction sets to be executed by a plurality of processors in a system, the process comprising: receiving a plurality of compiled executable instruction sets on a bus line connected to said processors; receiving workload data at a first processor of said plurality of processors, said workload data being representative of workload of each of the processors of said plurality; comparing the workload of each of the processors; modifying at least one compiled executable instruction set executable on at least one processor of the plurality by converting at least some instruction words of the at least one set into modified-instruction words executable on another processor of said plurality, said modifying including at least one operation selected from the group of: splitting said instruction words into modified-instruction words and managing a context of execution of the modified-instruction words by the another processor; and entering in the modified-instruction words no-operation instructions; and sending a signal from said first processor based on the data representative of the workload of each of the processors of said plurality to the bus line for modifying a number of executable instruction sets sent to each processor based on their respective workloads.

20. The process according to claim 19 wherein said workload data includes data regarding power consumption of each of said processors of said plurality.

21. The process according to claim 19 wherein said workload data includes data regarding memory usage of each of said processors of said plurality.

22. The process according to claim 19 wherein said workload data includes data regarding the number of operations carried out by each of said processors of said plurality.

23. The process of claim 19 , further comprising: managing a context of program execution for each of the processors in the plurality of processors.

24. The process of claim 19 wherein the modifying the at least one set of compiled instructions comprises splitting instruction words in the at least one set of compiled instructions into modified instruction words and each of the plurality of processors is of a very-long-instruction-word type.

25. The process of claim 19 wherein the modifying the at least one set of compiled instructions comprises adding no-operation instruction words to the instruction words in the set of compiled instructions.

26. The process of claim 19 wherein the modifying at least one compiled executable instruction set is performed using the first processor.

27. A system comprising: a plurality of processors configured to receive compiled instruction sets; and a bus system coupling a first processor of the plurality to each of the other processors within said plurality, said first processor configured to receive from each of the other processors data representative of a workload of the respective processor and based on the received data to: selectively modify a set of compiled instructions executable on at least one processor of the plurality by converting instruction words of the set into modified-instruction words executable on another processor of said plurality, said modifying including at least one operation selected from the group of: splitting said instruction words into modified-instruction words and managing a context of execution of the modified-instruction words by the another processor; and entering in the modified-instruction words no-operation instructions; and generate a control signal to control routing of compiled instruction sets to processors of the plurality.

28. The system according to claim 27 wherein said received data comprises power consumption data of each of said other processors of said plurality.

29. The system according to claim 27 wherein said received data comprises memory usage data of each of said other processors of said plurality.

30. The system according to claim 27 wherein said received data comprises a number of operations carried out by each of said other processors of said plurality.

31. The system of claim 27 wherein the first processor is configured to manage a context of program execution for each of the processors in the plurality of processors and each of the processors is a very-large-instruction-word processor.

32. The system of claim 27 wherein managing a context of program execution includes tracking addresses in a memory in which data and instructions are stored.