Method of forming high-k dual dielectric stack

1. A method comprising: providing a Group III-V component semiconductor material to form a transistor for CMOS technology; forming a first layer over said Group III-V component semiconductor material, said first layer comprising an oxide of gadolinium and an oxide of gallium, said first layer to prevent pining a Fermi level at said surface; forming in-situ a second layer over said first layer, said second layer for scaling an equivalent oxide thickness (EOT); annealing said first layer before or after forming said second layer to remove bulk trap defects in said first layer; and forming a gate electrode above said second layer over said first layer wherein said second layer is interposed between the first layer and the gate electrode.

2. The method of claim 1 wherein said first layer comprises a heterogeneous material.

3. The method of claim 1 wherein said first layer has a unit cell thickness.

4. The method of claim 1 wherein said forming of said first layer comprises a co-deposition of two or more different dielectric materials.

5. A method comprising: forming a Group III-V component semiconductor material; and forming a high-k dual dielectric stack over said Group III-V component semiconductor material, wherein said high-k dual dielectric stack comprises: a first layer the first layer comprising a heterogeneous material with discrete regions of oxides of gallium and oxides of gadolinium, said first layer to prevent pining a Fermi level at a surface of said Group III-V component semiconductor material; and a second layer disposed over said first layer, said second layer for scaling an equivalent oxide thickness (EOT); and forming a gate electrode above said second layer disposed over said first layer wherein said second layer is interposed between the first layer and the gate electrode.

6. The method of claim 5 wherein said first layer comprises a composite.

7. The method of claim 5 wherein said second layer comprises a high-k dielectric with an EOT of 1.00 nm.

8. The method of claim 5 wherein said high-k dual dielectric stack comprises an EOT of 2.00 nm.

9. A method comprising: forming a first layer comprising an oxide of gallium and an oxide of gadolinium over a Group III-V component semiconductor material; and forming a second layer consisting of silicon nitride directly on said first layer.

10. The method of claim 9 wherein said first layer is a monolayer thick.

11. The method of claim 9 wherein the first layer comprises Gadolinium Gallium Garnet (GGG).

12. The method of claim 9 wherein the equivalent oxide thickness (EOT) of said first layer and said second layer is between 2.5 to 2.8 nanometers.

13. The method of claim 9 wherein the equivalent oxide thickness (EOT) of said first layer and said second layer is about 2.0 nanometers.

14. The method of claim 9 wherein forming said first layer comprises co-depositing said oxide of gallium and said oxide of gadolinium.

15. The method of claim 14 wherein said oxide of gallium and said oxide of gadolinium are formed by e-beam evaporation.

16. The method of claim 9 wherein said second layer is formed by jet vapor deposition.

17. The method of claim 9 further comprising annealing said first layer prior to forming said second layer.

18. The method of claim 9 , after forming said second layer annealing said first layer.

19. The method of claim 9 further comprising forming gate electrode above second layer.