A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory system comprising; a board; a first memory chip attached to a first surface of the board and having a first electrode pad that is connected to a first clock signal line that carries a first clock signal transmitted to the first memory chip; and a second memory chip attached to a second surface of the board, wherein the second memory chip comprising a second electrode pad that is connected to the first electrode pad by a through-electrode extending through the board, and a first switching unit that switches to electrically connect the second electrode pad to an integrated circuit in response to a first level of a control signal to transmit the first clock signal from the second electrode pad to the integrated circuit.
2. The memory system of claim 1 , where in the second memory chip further comprising: a third electrode pad that is connected to a second clock signal line that carries a second clock signal to the second memory chip, a second switching unit that switches to electrically connect the third electrode pad to the integrated circuit in response to a second level of the control signal to transmit the second clock signal from the third electrode pad to the integrated circuit.
3. The memory system of claim 1 , wherein the control signal is a mirroring signal.
4. The memory system of claim 1 , wherein the first clock signal and the second clock signals are data clock signals.
5. The memory system of claim 4 , wherein the data clock signals are WCK signals.
6. The memory system of claim 4 , wherein the data clock signal is a WCK 01 or a WCK 23 signal.
7. The memory system of claim 1 , the second chip operates in x16 mode when the integrated circuit receives the first clock signal through the second electrode pad.
8. The memory system of claim 2 , the second chip operates in x32 mode when the integrated circuit receives the second clock signal through the third electrode pad.
9. The memory system of claim 1 , wherein the second electrode pad is located at a mirroring site of the first electrode pad.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 25, 2011
May 15, 2012
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.